* [PATCH v3 1/8] target/tricore: Introduce ISA 1.6.2 feature
2023-06-14 10:00 [PATCH v3 0/8] TriCore 1.6.2 Instructions Bastian Koppelmann
@ 2023-06-14 10:00 ` Bastian Koppelmann
2023-06-14 10:00 ` [PATCH v3 2/8] target/tricore: Add popcnt.w insn Bastian Koppelmann
` (6 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Bastian Koppelmann @ 2023-06-14 10:00 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, richard.henderson
we also introduce the tc37x CPU that implements that ISA version.
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/cpu.c | 13 +++++++++++++
target/tricore/cpu.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 7fa113fed2..f15169bd1b 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -104,6 +104,10 @@ static void tricore_cpu_realizefn(DeviceState *dev, Error **errp)
}
/* Some features automatically imply others */
+ if (tricore_feature(env, TRICORE_FEATURE_162)) {
+ set_feature(env, TRICORE_FEATURE_161);
+ }
+
if (tricore_feature(env, TRICORE_FEATURE_161)) {
set_feature(env, TRICORE_FEATURE_16);
}
@@ -164,6 +168,14 @@ static void tc27x_initfn(Object *obj)
set_feature(&cpu->env, TRICORE_FEATURE_161);
}
+static void tc37x_initfn(Object *obj)
+{
+ TriCoreCPU *cpu = TRICORE_CPU(obj);
+
+ set_feature(&cpu->env, TRICORE_FEATURE_162);
+}
+
+
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps tricore_sysemu_ops = {
@@ -226,6 +238,7 @@ static const TypeInfo tricore_cpu_type_infos[] = {
DEFINE_TRICORE_CPU_TYPE("tc1796", tc1796_initfn),
DEFINE_TRICORE_CPU_TYPE("tc1797", tc1797_initfn),
DEFINE_TRICORE_CPU_TYPE("tc27x", tc27x_initfn),
+ DEFINE_TRICORE_CPU_TYPE("tc37x", tc37x_initfn),
};
DEFINE_TYPES(tricore_cpu_type_infos)
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index d98a3fb671..041fc0b6e5 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -273,6 +273,7 @@ enum tricore_features {
TRICORE_FEATURE_131,
TRICORE_FEATURE_16,
TRICORE_FEATURE_161,
+ TRICORE_FEATURE_162,
};
static inline int tricore_feature(CPUTriCoreState *env, int feature)
--
2.40.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v3 2/8] target/tricore: Add popcnt.w insn
2023-06-14 10:00 [PATCH v3 0/8] TriCore 1.6.2 Instructions Bastian Koppelmann
2023-06-14 10:00 ` [PATCH v3 1/8] target/tricore: Introduce ISA 1.6.2 feature Bastian Koppelmann
@ 2023-06-14 10:00 ` Bastian Koppelmann
2023-06-14 10:00 ` [PATCH v3 3/8] target/tricore: Add LHA insn Bastian Koppelmann
` (5 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Bastian Koppelmann @ 2023-06-14 10:00 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, richard.henderson
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 7 +++++++
target/tricore/tricore-opcodes.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index cd33a1dcdd..26b284bcec 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6197,6 +6197,13 @@ static void decode_rr_divide(DisasContext *ctx)
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
+ case OPC2_32_RR_POPCNT_W:
+ if (has_feature(ctx, TRICORE_FEATURE_162)) {
+ tcg_gen_ctpop_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
+ break;
case OPC2_32_RR_DIV:
if (has_feature(ctx, TRICORE_FEATURE_16)) {
GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h
index f7135f183d..59aa39a7a5 100644
--- a/target/tricore/tricore-opcodes.h
+++ b/target/tricore/tricore-opcodes.h
@@ -1133,6 +1133,7 @@ enum {
OPC2_32_RR_PARITY = 0x02,
OPC2_32_RR_UNPACK = 0x08,
OPC2_32_RR_CRC32 = 0x03,
+ OPC2_32_RR_POPCNT_W = 0x22, /* 1.6.2 only */
OPC2_32_RR_DIV = 0x20,
OPC2_32_RR_DIV_U = 0x21,
OPC2_32_RR_MUL_F = 0x04,
--
2.40.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v3 3/8] target/tricore: Add LHA insn
2023-06-14 10:00 [PATCH v3 0/8] TriCore 1.6.2 Instructions Bastian Koppelmann
2023-06-14 10:00 ` [PATCH v3 1/8] target/tricore: Introduce ISA 1.6.2 feature Bastian Koppelmann
2023-06-14 10:00 ` [PATCH v3 2/8] target/tricore: Add popcnt.w insn Bastian Koppelmann
@ 2023-06-14 10:00 ` Bastian Koppelmann
2023-06-14 10:00 ` [PATCH v3 4/8] target/tricore: Add crc32l.w insn Bastian Koppelmann
` (4 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Bastian Koppelmann @ 2023-06-14 10:00 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, richard.henderson
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 14 ++++++++++++--
target/tricore/tricore-opcodes.h | 9 ++++++++-
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 26b284bcec..898557d22a 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -7931,7 +7931,7 @@ static void decode_sys_interrupts(DisasContext *ctx)
static void decode_32Bit_opc(DisasContext *ctx)
{
- int op1;
+ int op1, op2;
int32_t r1, r2, r3;
int32_t address, const16;
int8_t b, const4;
@@ -7982,9 +7982,19 @@ static void decode_32Bit_opc(DisasContext *ctx)
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
break;
- case OPC1_32_ABS_LEA:
+ case OPCM_32_ABS_LEA_LHA:
address = MASK_OP_ABS_OFF18(ctx->opcode);
r1 = MASK_OP_ABS_S1D(ctx->opcode);
+
+ if (has_feature(ctx, TRICORE_FEATURE_162)) {
+ op2 = MASK_OP_ABS_OP2(ctx->opcode);
+ if (op2 == OPC2_32_ABS_LHA) {
+ tcg_gen_movi_tl(cpu_gpr_a[r1], address << 14);
+ break;
+ }
+ /* otherwise translate regular LEA */
+ }
+
tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address));
break;
/* ABSB-format */
diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h
index 59aa39a7a5..9fab4bd75c 100644
--- a/target/tricore/tricore-opcodes.h
+++ b/target/tricore/tricore-opcodes.h
@@ -430,7 +430,7 @@ enum {
OPCM_32_ABS_STOREB_H = 0x25,
OPC1_32_ABS_STOREQ = 0x65,
OPC1_32_ABS_LD_Q = 0x45,
- OPC1_32_ABS_LEA = 0xc5,
+ OPCM_32_ABS_LEA_LHA = 0xc5,
/* ABSB Format */
OPC1_32_ABSB_ST_T = 0xd5,
/* B Format */
@@ -592,6 +592,13 @@ enum {
OPC2_32_ABS_ST_B = 0x00,
OPC2_32_ABS_ST_H = 0x02,
};
+
+/* OPCM_32_ABS_LEA_LHA */
+enum {
+ OPC2_32_ABS_LEA = 0x00,
+ OPC2_32_ABS_LHA = 0x01,
+};
+
/*
* Bit Format
*/
--
2.40.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v3 4/8] target/tricore: Add crc32l.w insn
2023-06-14 10:00 [PATCH v3 0/8] TriCore 1.6.2 Instructions Bastian Koppelmann
` (2 preceding siblings ...)
2023-06-14 10:00 ` [PATCH v3 3/8] target/tricore: Add LHA insn Bastian Koppelmann
@ 2023-06-14 10:00 ` Bastian Koppelmann
2023-06-14 10:00 ` [PATCH v3 5/8] target/tricore: Add crc32.b insn Bastian Koppelmann
` (3 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Bastian Koppelmann @ 2023-06-14 10:00 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, richard.henderson
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/helper.h | 3 ++-
target/tricore/op_helper.c | 10 +++++++++-
target/tricore/translate.c | 12 ++++++++++--
target/tricore/tricore-opcodes.h | 3 ++-
4 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index b64780c37d..24da5e97c0 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -131,7 +131,8 @@ DEF_HELPER_FLAGS_5(mul_h, TCG_CALL_NO_RWG_SE, i64, i32, i32, i32, i32, i32)
DEF_HELPER_FLAGS_5(mulm_h, TCG_CALL_NO_RWG_SE, i64, i32, i32, i32, i32, i32)
DEF_HELPER_FLAGS_5(mulr_h, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32, i32, i32)
/* crc32 */
-DEF_HELPER_FLAGS_2(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32)
+DEF_HELPER_FLAGS_2(crc32_be, TCG_CALL_NO_RWG_SE, i32, i32, i32)
+DEF_HELPER_FLAGS_2(crc32_le, TCG_CALL_NO_RWG_SE, i32, i32, i32)
/* CSA */
DEF_HELPER_2(call, void, env, i32)
DEF_HELPER_1(ret, void, env)
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index 54f54811d9..8ce404cb93 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -2284,7 +2284,7 @@ uint32_t helper_mulr_h(uint32_t arg00, uint32_t arg01,
return (result1 & 0xffff0000) | (result0 >> 16);
}
-uint32_t helper_crc32(uint32_t arg0, uint32_t arg1)
+uint32_t helper_crc32_be(uint32_t arg0, uint32_t arg1)
{
uint8_t buf[4];
stl_be_p(buf, arg0);
@@ -2292,6 +2292,14 @@ uint32_t helper_crc32(uint32_t arg0, uint32_t arg1)
return crc32(arg1, buf, 4);
}
+uint32_t helper_crc32_le(uint32_t arg0, uint32_t arg1)
+{
+ uint8_t buf[4];
+ stl_le_p(buf, arg0);
+
+ return crc32(arg1, buf, 4);
+}
+
/* context save area (CSA) related helpers */
static int cdc_increment(target_ulong *psw)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 898557d22a..250de80de5 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6190,13 +6190,21 @@ static void decode_rr_divide(DisasContext *ctx)
CHECK_REG_PAIR(r3);
gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
break;
- case OPC2_32_RR_CRC32:
+ case OPC2_32_RR_CRC32: /* CRC32B.W in 1.6.2 */
if (has_feature(ctx, TRICORE_FEATURE_161)) {
- gen_helper_crc32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ gen_helper_crc32_be(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
+ case OPC2_32_RR_CRC32L_W:
+ if (has_feature(ctx, TRICORE_FEATURE_162)) {
+ gen_helper_crc32_le(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
+ break;
+
case OPC2_32_RR_POPCNT_W:
if (has_feature(ctx, TRICORE_FEATURE_162)) {
tcg_gen_ctpop_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h
index 9fab4bd75c..be07f82ec1 100644
--- a/target/tricore/tricore-opcodes.h
+++ b/target/tricore/tricore-opcodes.h
@@ -1139,7 +1139,8 @@ enum {
OPC2_32_RR_DVINIT_U = 0x0a,
OPC2_32_RR_PARITY = 0x02,
OPC2_32_RR_UNPACK = 0x08,
- OPC2_32_RR_CRC32 = 0x03,
+ OPC2_32_RR_CRC32 = 0x03, /* CRC32B.W in 1.6.2 */
+ OPC2_32_RR_CRC32L_W = 0x07, /* 1.6.2 only */
OPC2_32_RR_POPCNT_W = 0x22, /* 1.6.2 only */
OPC2_32_RR_DIV = 0x20,
OPC2_32_RR_DIV_U = 0x21,
--
2.40.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v3 5/8] target/tricore: Add crc32.b insn
2023-06-14 10:00 [PATCH v3 0/8] TriCore 1.6.2 Instructions Bastian Koppelmann
` (3 preceding siblings ...)
2023-06-14 10:00 ` [PATCH v3 4/8] target/tricore: Add crc32l.w insn Bastian Koppelmann
@ 2023-06-14 10:00 ` Bastian Koppelmann
2023-06-14 10:00 ` [PATCH v3 6/8] target/tricore: Add shuffle insn Bastian Koppelmann
` (2 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Bastian Koppelmann @ 2023-06-14 10:00 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, richard.henderson
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/helper.h | 1 +
target/tricore/op_helper.c | 8 ++++++++
target/tricore/translate.c | 7 +++++++
target/tricore/tricore-opcodes.h | 1 +
4 files changed, 17 insertions(+)
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index 24da5e97c0..a10576e09e 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -131,6 +131,7 @@ DEF_HELPER_FLAGS_5(mul_h, TCG_CALL_NO_RWG_SE, i64, i32, i32, i32, i32, i32)
DEF_HELPER_FLAGS_5(mulm_h, TCG_CALL_NO_RWG_SE, i64, i32, i32, i32, i32, i32)
DEF_HELPER_FLAGS_5(mulr_h, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32, i32, i32)
/* crc32 */
+DEF_HELPER_FLAGS_2(crc32b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
DEF_HELPER_FLAGS_2(crc32_be, TCG_CALL_NO_RWG_SE, i32, i32, i32)
DEF_HELPER_FLAGS_2(crc32_le, TCG_CALL_NO_RWG_SE, i32, i32, i32)
/* CSA */
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index 8ce404cb93..b6ef1462e4 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -2284,6 +2284,14 @@ uint32_t helper_mulr_h(uint32_t arg00, uint32_t arg01,
return (result1 & 0xffff0000) | (result0 >> 16);
}
+uint32_t helper_crc32b(uint32_t arg0, uint32_t arg1)
+{
+ uint8_t buf[1] = { arg0 & 0xff };
+
+ return crc32(arg1, buf, 1);
+}
+
+
uint32_t helper_crc32_be(uint32_t arg0, uint32_t arg1)
{
uint8_t buf[4];
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 250de80de5..85526ef4db 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6190,6 +6190,13 @@ static void decode_rr_divide(DisasContext *ctx)
CHECK_REG_PAIR(r3);
gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
break;
+ case OPC2_32_RR_CRC32_B:
+ if (has_feature(ctx, TRICORE_FEATURE_162)) {
+ gen_helper_crc32b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
+ break;
case OPC2_32_RR_CRC32: /* CRC32B.W in 1.6.2 */
if (has_feature(ctx, TRICORE_FEATURE_161)) {
gen_helper_crc32_be(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h
index be07f82ec1..27f80e1702 100644
--- a/target/tricore/tricore-opcodes.h
+++ b/target/tricore/tricore-opcodes.h
@@ -1140,6 +1140,7 @@ enum {
OPC2_32_RR_PARITY = 0x02,
OPC2_32_RR_UNPACK = 0x08,
OPC2_32_RR_CRC32 = 0x03, /* CRC32B.W in 1.6.2 */
+ OPC2_32_RR_CRC32_B = 0x06, /* 1.6.2 only */
OPC2_32_RR_CRC32L_W = 0x07, /* 1.6.2 only */
OPC2_32_RR_POPCNT_W = 0x22, /* 1.6.2 only */
OPC2_32_RR_DIV = 0x20,
--
2.40.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v3 6/8] target/tricore: Add shuffle insn
2023-06-14 10:00 [PATCH v3 0/8] TriCore 1.6.2 Instructions Bastian Koppelmann
` (4 preceding siblings ...)
2023-06-14 10:00 ` [PATCH v3 5/8] target/tricore: Add crc32.b insn Bastian Koppelmann
@ 2023-06-14 10:00 ` Bastian Koppelmann
2023-06-14 10:00 ` [PATCH v3 7/8] target/tricore: Implement SYCSCALL insn Bastian Koppelmann
2023-06-14 10:00 ` [PATCH v3 8/8] target/tricore: Add DISABLE insn variant Bastian Koppelmann
7 siblings, 0 replies; 11+ messages in thread
From: Bastian Koppelmann @ 2023-06-14 10:00 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, richard.henderson
this is based on code by volumit (https://github.com/volumit/qemu/)
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/helper.h | 1 +
target/tricore/op_helper.c | 36 ++++++++++++++++++++++++++++++++
target/tricore/translate.c | 8 +++++++
target/tricore/tricore-opcodes.h | 1 +
4 files changed, 46 insertions(+)
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index a10576e09e..31d71eac7a 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -134,6 +134,7 @@ DEF_HELPER_FLAGS_5(mulr_h, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32, i32, i32)
DEF_HELPER_FLAGS_2(crc32b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
DEF_HELPER_FLAGS_2(crc32_be, TCG_CALL_NO_RWG_SE, i32, i32, i32)
DEF_HELPER_FLAGS_2(crc32_le, TCG_CALL_NO_RWG_SE, i32, i32, i32)
+DEF_HELPER_FLAGS_2(shuffle, TCG_CALL_NO_RWG_SE, i32, i32, i32)
/* CSA */
DEF_HELPER_2(call, void, env, i32)
DEF_HELPER_1(ret, void, env)
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index b6ef1462e4..026e15f3e0 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -2308,6 +2308,42 @@ uint32_t helper_crc32_le(uint32_t arg0, uint32_t arg1)
return crc32(arg1, buf, 4);
}
+uint32_t helper_shuffle(uint32_t arg0, uint32_t arg1)
+{
+ uint32_t resb;
+ uint32_t byte_select;
+ uint32_t res = 0;
+
+ byte_select = arg1 & 0x3;
+ resb = extract32(arg0, byte_select * 8, 8);
+ res |= resb << 0;
+
+ byte_select = (arg1 >> 2) & 0x3;
+ resb = extract32(arg0, byte_select * 8, 8);
+ res |= resb << 8;
+
+ byte_select = (arg1 >> 4) & 0x3;
+ resb = extract32(arg0, byte_select * 8, 8);
+ res |= resb << 16;
+
+ byte_select = (arg1 >> 6) & 0x3;
+ resb = extract32(arg0, byte_select * 8, 8);
+ res |= resb << 24;
+
+ if (arg1 & 0x100) {
+ /* Assign the correct nibble position. */
+ res = ((res & 0xf0f0f0f0) >> 4)
+ | ((res & 0x0f0f0f0f) << 4);
+ /* Assign the correct bit position. */
+ res = ((res & 0x88888888) >> 3)
+ | ((res & 0x44444444) >> 1)
+ | ((res & 0x22222222) << 1)
+ | ((res & 0x11111111) << 3);
+ }
+
+ return res;
+}
+
/* context save area (CSA) related helpers */
static int cdc_increment(target_ulong *psw)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 85526ef4db..a4c60e8ae2 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -5011,6 +5011,14 @@ static void decode_rc_logical_shift(DisasContext *ctx)
case OPC2_32_RC_XOR:
tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
+ case OPC2_32_RC_SHUFFLE:
+ if (has_feature(ctx, TRICORE_FEATURE_162)) {
+ TCGv temp = tcg_constant_i32(const9);
+ gen_helper_shuffle(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
+ break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h
index 27f80e1702..af63926731 100644
--- a/target/tricore/tricore-opcodes.h
+++ b/target/tricore/tricore-opcodes.h
@@ -885,6 +885,7 @@ enum {
OPC2_32_RC_SHAS = 0x02,
OPC2_32_RC_XNOR = 0x0d,
OPC2_32_RC_XOR = 0x0c,
+ OPC2_32_RC_SHUFFLE = 0x07, /* v1.6.2 only */
};
/* OPCM_32_RC_ACCUMULATOR */
enum {
--
2.40.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v3 7/8] target/tricore: Implement SYCSCALL insn
2023-06-14 10:00 [PATCH v3 0/8] TriCore 1.6.2 Instructions Bastian Koppelmann
` (5 preceding siblings ...)
2023-06-14 10:00 ` [PATCH v3 6/8] target/tricore: Add shuffle insn Bastian Koppelmann
@ 2023-06-14 10:00 ` Bastian Koppelmann
2023-06-14 12:04 ` Richard Henderson
2023-06-14 10:00 ` [PATCH v3 8/8] target/tricore: Add DISABLE insn variant Bastian Koppelmann
7 siblings, 1 reply; 11+ messages in thread
From: Bastian Koppelmann @ 2023-06-14 10:00 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, richard.henderson
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1452
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index a4c60e8ae2..f01000efd4 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -5236,7 +5236,7 @@ static void decode_rc_serviceroutine(DisasContext *ctx)
gen_helper_1arg(bisr, const9);
break;
case OPC2_32_RC_SYSCALL:
- /* TODO: Add exception generation */
+ generate_trap(ctx, TRAPC_SYSCALL, const9 & 0xff);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
--
2.40.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v3 8/8] target/tricore: Add DISABLE insn variant
2023-06-14 10:00 [PATCH v3 0/8] TriCore 1.6.2 Instructions Bastian Koppelmann
` (6 preceding siblings ...)
2023-06-14 10:00 ` [PATCH v3 7/8] target/tricore: Implement SYCSCALL insn Bastian Koppelmann
@ 2023-06-14 10:00 ` Bastian Koppelmann
2023-06-14 12:11 ` Richard Henderson
7 siblings, 1 reply; 11+ messages in thread
From: Bastian Koppelmann @ 2023-06-14 10:00 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, richard.henderson
this variant saves the 'IE' bit to a 'd' register. The 'IE' bitfield
changed from ISA version 1.6.1, so we add icr_ie_offset to DisasContext
as with the other DISABLE insn.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 11 ++++++++++-
target/tricore/tricore-opcodes.h | 1 +
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index f01000efd4..6712d98f6e 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -75,7 +75,7 @@ typedef struct DisasContext {
int mem_idx;
uint32_t hflags, saved_hflags;
uint64_t features;
- uint32_t icr_ie_mask;
+ uint32_t icr_ie_mask, icr_ie_offset;
} DisasContext;
static int has_feature(DisasContext *ctx, int feature)
@@ -7883,6 +7883,13 @@ static void decode_sys_interrupts(DisasContext *ctx)
case OPC2_32_SYS_DISABLE:
tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask);
break;
+ case OPC2_32_SYS_DISABLE_D:
+ if (has_feature(ctx, TRICORE_FEATURE_16)) {
+ tcg_gen_extract_tl(cpu_gpr_d[r1], cpu_ICR, ctx->icr_ie_offset, 1);
+ tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask);
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
case OPC2_32_SYS_DSYNC:
break;
case OPC2_32_SYS_ENABLE:
@@ -8302,8 +8309,10 @@ static void tricore_tr_init_disas_context(DisasContextBase *dcbase,
ctx->features = env->features;
if (has_feature(ctx, TRICORE_FEATURE_161)) {
ctx->icr_ie_mask = R_ICR_IE_161_MASK;
+ ctx->icr_ie_offset = R_ICR_IE_161_SHIFT;
} else {
ctx->icr_ie_mask = R_ICR_IE_13_MASK;
+ ctx->icr_ie_offset = R_ICR_IE_13_SHIFT;
}
}
diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h
index af63926731..bc62b73173 100644
--- a/target/tricore/tricore-opcodes.h
+++ b/target/tricore/tricore-opcodes.h
@@ -1467,6 +1467,7 @@ enum {
enum {
OPC2_32_SYS_DEBUG = 0x04,
OPC2_32_SYS_DISABLE = 0x0d,
+ OPC2_32_SYS_DISABLE_D = 0x0f, /* 1.6 up */
OPC2_32_SYS_DSYNC = 0x12,
OPC2_32_SYS_ENABLE = 0x0c,
OPC2_32_SYS_ISYNC = 0x13,
--
2.40.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v3 8/8] target/tricore: Add DISABLE insn variant
2023-06-14 10:00 ` [PATCH v3 8/8] target/tricore: Add DISABLE insn variant Bastian Koppelmann
@ 2023-06-14 12:11 ` Richard Henderson
0 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2023-06-14 12:11 UTC (permalink / raw)
To: Bastian Koppelmann, qemu-devel
On 6/14/23 12:00, Bastian Koppelmann wrote:
> this variant saves the 'IE' bit to a 'd' register. The 'IE' bitfield
> changed from ISA version 1.6.1, so we add icr_ie_offset to DisasContext
> as with the other DISABLE insn.
>
> Signed-off-by: Bastian Koppelmann<kbastian@mail.uni-paderborn.de>
> ---
> target/tricore/translate.c | 11 ++++++++++-
> target/tricore/tricore-opcodes.h | 1 +
> 2 files changed, 11 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 11+ messages in thread