From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Cc: kbastian@mail.uni-paderborn.de, richard.henderson@linaro.org
Subject: [PATCH 0/4] TriCore Privilege Levels
Date: Wed, 14 Jun 2023 18:59:30 +0200 [thread overview]
Message-ID: <20230614165934.1370440-1-kbastian@mail.uni-paderborn.de> (raw)
Hi,
this patch series tries to properly implement privilege levels for the TriCore,
as discussed in
https://lore.kernel.org/qemu-devel/20230118090319.32n4uto7ogy3gfr6@schnipp.zuhause/.
While implementing privilege traps for the SV/UM1 only insns, I saw that
the RESTORE insn uses the wrong ICR.IE bit. So I fixed that as well.
Cheers,
Bastian
Bastian Koppelmann (4):
target/tricore: Introduce priv tb flag
target/tricore: Implement privilege level for all insns
target/tricore: Honour privilege changes on PSW write
target/tricore: Fix ICR.IE offset in RESTORE insn
target/tricore/cpu.h | 17 +++++++----
target/tricore/op_helper.c | 11 +++++++
target/tricore/translate.c | 61 ++++++++++++++++++++++++++++----------
3 files changed, 68 insertions(+), 21 deletions(-)
--
2.40.1
next reply other threads:[~2023-06-14 17:00 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-14 16:59 Bastian Koppelmann [this message]
2023-06-14 16:59 ` [PATCH 1/4] target/tricore: Introduce priv tb flag Bastian Koppelmann
2023-06-15 5:18 ` Richard Henderson
2023-06-14 16:59 ` [PATCH 2/4] target/tricore: Implement privilege level for all insns Bastian Koppelmann
2023-06-15 5:20 ` Richard Henderson
2023-06-14 16:59 ` [PATCH 3/4] target/tricore: Honour privilege changes on PSW write Bastian Koppelmann
2023-06-15 7:37 ` Richard Henderson
2023-06-15 15:15 ` Bastian Koppelmann
2023-06-15 15:36 ` Bastian Koppelmann
2023-06-14 16:59 ` [PATCH 4/4] target/tricore: Fix ICR.IE offset in RESTORE insn Bastian Koppelmann
2023-06-15 7:39 ` Richard Henderson
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