From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Cc: kbastian@mail.uni-paderborn.de, richard.henderson@linaro.org
Subject: [PATCH 2/4] target/tricore: Implement privilege level for all insns
Date: Wed, 14 Jun 2023 18:59:32 +0200 [thread overview]
Message-ID: <20230614165934.1370440-3-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <20230614165934.1370440-1-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 41 +++++++++++++++++++++++++++++---------
1 file changed, 32 insertions(+), 9 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index a0644dd120..edbc319fa1 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -385,7 +385,7 @@ static inline void gen_mtcr(DisasContext *ctx, TCGv r1,
}
}
} else {
- /* generate privilege trap */
+ generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
}
}
@@ -3372,7 +3372,11 @@ static void decode_sc_opc(DisasContext *ctx, int op1)
tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
break;
case OPC1_16_SC_BISR:
- gen_helper_1arg(bisr, const16 & 0xff);
+ if (ctx->priv == TRICORE_PRIV_SM) {
+ gen_helper_1arg(bisr, const16 & 0xff);
+ } else {
+ generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
+ }
break;
case OPC1_16_SC_LD_A:
gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
@@ -5234,7 +5238,11 @@ static void decode_rc_serviceroutine(DisasContext *ctx)
switch (op2) {
case OPC2_32_RC_BISR:
- gen_helper_1arg(bisr, const9);
+ if (ctx->priv == TRICORE_PRIV_SM) {
+ gen_helper_1arg(bisr, const9);
+ } else {
+ generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
+ }
break;
case OPC2_32_RC_SYSCALL:
generate_trap(ctx, TRAPC_SYSCALL, const9 & 0xff);
@@ -7882,19 +7890,32 @@ static void decode_sys_interrupts(DisasContext *ctx)
/* raise EXCP_DEBUG */
break;
case OPC2_32_SYS_DISABLE:
- tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask);
+ if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) {
+ tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask);
+ } else {
+ generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
+ }
break;
case OPC2_32_SYS_DISABLE_D:
if (has_feature(ctx, TRICORE_FEATURE_16)) {
- tcg_gen_extract_tl(cpu_gpr_d[r1], cpu_ICR, ctx->icr_ie_offset, 1);
- tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask);
+ if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) {
+ tcg_gen_extract_tl(cpu_gpr_d[r1], cpu_ICR,
+ ctx->icr_ie_offset, 1);
+ tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask);
+ } else {
+ generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
+ }
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
case OPC2_32_SYS_DSYNC:
break;
case OPC2_32_SYS_ENABLE:
- tcg_gen_ori_tl(cpu_ICR, cpu_ICR, ctx->icr_ie_mask);
+ if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) {
+ tcg_gen_ori_tl(cpu_ICR, cpu_ICR, ctx->icr_ie_mask);
+ } else {
+ generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
+ }
break;
case OPC2_32_SYS_ISYNC:
break;
@@ -7924,7 +7945,7 @@ static void decode_sys_interrupts(DisasContext *ctx)
tcg_gen_exit_tb(NULL, 0);
ctx->base.is_jmp = DISAS_NORETURN;
} else {
- /* generate privilege trap */
+ generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
}
break;
case OPC2_32_SYS_RSLCX:
@@ -7937,7 +7958,9 @@ static void decode_sys_interrupts(DisasContext *ctx)
if (has_feature(ctx, TRICORE_FEATURE_16)) {
if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) {
tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1);
- } /* else raise privilege trap */
+ } else {
+ generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
+ }
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
--
2.40.1
next prev parent reply other threads:[~2023-06-14 17:00 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-14 16:59 [PATCH 0/4] TriCore Privilege Levels Bastian Koppelmann
2023-06-14 16:59 ` [PATCH 1/4] target/tricore: Introduce priv tb flag Bastian Koppelmann
2023-06-15 5:18 ` Richard Henderson
2023-06-14 16:59 ` Bastian Koppelmann [this message]
2023-06-15 5:20 ` [PATCH 2/4] target/tricore: Implement privilege level for all insns Richard Henderson
2023-06-14 16:59 ` [PATCH 3/4] target/tricore: Honour privilege changes on PSW write Bastian Koppelmann
2023-06-15 7:37 ` Richard Henderson
2023-06-15 15:15 ` Bastian Koppelmann
2023-06-15 15:36 ` Bastian Koppelmann
2023-06-14 16:59 ` [PATCH 4/4] target/tricore: Fix ICR.IE offset in RESTORE insn Bastian Koppelmann
2023-06-15 7:39 ` Richard Henderson
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