From: Weiwei Li <liweiwei@iscas.ac.cn>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn,
lazyparser@gmail.com, Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [PATCH v2 1/6] target/riscv: Add properties for BF16 extensions
Date: Thu, 15 Jun 2023 14:32:57 +0800 [thread overview]
Message-ID: <20230615063302.102409-2-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20230615063302.102409-1-liweiwei@iscas.ac.cn>
Add ext_zfbfmin/zvfbfmin/zvfbfwma properties.
Add require check for BF16 extensions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 20 ++++++++++++++++++++
target/riscv/cpu_cfg.h | 3 +++
2 files changed, 23 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 881bddf393..dc6b2f72f6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1059,6 +1059,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
+ if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) {
+ error_setg(errp, "Zfbfmin extension depends on F extension");
+ return;
+ }
+
if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
error_setg(errp, "D extension requires F extension");
return;
@@ -1109,6 +1114,21 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
+ if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) {
+ error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension");
+ return;
+ }
+
+ if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) {
+ error_setg(errp, "Zvfbfmin extension depends on Zve32f extension");
+ return;
+ }
+
+ if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) {
+ error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension");
+ return;
+ }
+
/* Set the ISA extensions, checks should have happened above */
if (cpu->cfg.ext_zhinx) {
cpu->cfg.ext_zhinxmin = true;
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index c4a627d335..7d16f32720 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -75,6 +75,7 @@ struct RISCVCPUConfig {
bool ext_svpbmt;
bool ext_zdinx;
bool ext_zawrs;
+ bool ext_zfbfmin;
bool ext_zfh;
bool ext_zfhmin;
bool ext_zfinx;
@@ -84,6 +85,8 @@ struct RISCVCPUConfig {
bool ext_zve64f;
bool ext_zve64d;
bool ext_zmmul;
+ bool ext_zvfbfmin;
+ bool ext_zvfbfwma;
bool ext_zvfh;
bool ext_zvfhmin;
bool ext_smaia;
--
2.25.1
next prev parent reply other threads:[~2023-06-15 6:34 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-15 6:32 [PATCH v2 0/6] target/riscv: Add support for BF16 extensions Weiwei Li
2023-06-15 6:32 ` Weiwei Li [this message]
2023-06-15 12:58 ` [PATCH v2 1/6] target/riscv: Add properties " Rob Bradford
2023-06-15 13:14 ` Weiwei Li
2023-06-15 15:00 ` Rob Bradford
2023-07-03 3:05 ` Alistair Francis
2023-06-15 6:32 ` [PATCH v2 2/6] target/riscv: Add support for Zfbfmin extension Weiwei Li
2023-06-15 6:32 ` [PATCH v2 3/6] target/riscv: Add support for Zvfbfmin extension Weiwei Li
2023-06-15 6:33 ` [PATCH v2 4/6] target/riscv: Add support for Zvfbfwma extension Weiwei Li
2023-06-15 6:33 ` [PATCH v2 5/6] target/riscv: Expose properties for BF16 extensions Weiwei Li
2023-06-15 6:33 ` [PATCH v2 6/6] target/riscv: Add disas support " Weiwei Li
2023-07-03 3:08 ` Alistair Francis
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