* [PATCH 0/1] Secondary Cadence GEM IRQs @ 2023-06-15 13:48 Kinsey Moore 2023-06-15 13:48 ` [PATCH] hw/arm/xlnx: Connect secondary CGEM IRQs Kinsey Moore 0 siblings, 1 reply; 4+ messages in thread From: Kinsey Moore @ 2023-06-15 13:48 UTC (permalink / raw) To: qemu-devel In testing RTEMS on the ZynqMP platform, I noticed that priority queues were not functioning properly. I tracked this down to an unconnected interrupt source in the Cadence GEM when multiple priority queues are configured. I'm not sure if the Cadence IP can actually be configured for separate interrupt sources per queue, so I opted to leave the multiple IRQ sources intact and connect the additional sources on platforms that need it. If it makes more sense to route all interrutps for this peripheral through a single interrupt source, I can submit that patch instead. ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH] hw/arm/xlnx: Connect secondary CGEM IRQs 2023-06-15 13:48 [PATCH 0/1] Secondary Cadence GEM IRQs Kinsey Moore @ 2023-06-15 13:48 ` Kinsey Moore 2023-06-16 8:27 ` Francisco Iglesias 0 siblings, 1 reply; 4+ messages in thread From: Kinsey Moore @ 2023-06-15 13:48 UTC (permalink / raw) To: qemu-devel; +Cc: Kinsey Moore The Cadence GEM peripherals as configured for Zynq MPSoC and Versal platforms have two priority queues with separate interrupt sources for each. If the interrupt source for the second priority queue is not connected, they work in polling mode only. This change connects the second interrupt source for platforms where it is available. This patch has been tested using the lwIP stack with a Xilinx-supplied driver from their embeddedsw repository. Signed-off-by: Kinsey Moore <kinsey.moore@oarcorp.com> --- hw/arm/xlnx-versal.c | 1 + hw/arm/xlnx-zynqmp.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 60bf5fe657..a9e06b7fd1 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -272,6 +272,7 @@ static void versal_create_gems(Versal *s, qemu_irq *pic) memory_region_add_subregion(&s->mr_ps, addrs[i], mr); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[irqs[i]]); g_free(name); } } diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 5905a33015..b919b38e91 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -635,6 +635,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, gic_spi[gem_intr[i]]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 1, + gic_spi[gem_intr[i]]); } for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { -- 2.30.2 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] hw/arm/xlnx: Connect secondary CGEM IRQs 2023-06-15 13:48 ` [PATCH] hw/arm/xlnx: Connect secondary CGEM IRQs Kinsey Moore @ 2023-06-16 8:27 ` Francisco Iglesias 2023-06-16 14:08 ` Kinsey Moore 0 siblings, 1 reply; 4+ messages in thread From: Francisco Iglesias @ 2023-06-16 8:27 UTC (permalink / raw) To: Kinsey Moore; +Cc: qemu-devel Hi Kinsey, On [2023 Jun 15] Thu 08:48:47, Kinsey Moore wrote: > The Cadence GEM peripherals as configured for Zynq MPSoC and Versal > platforms have two priority queues with separate interrupt sources for > each. If the interrupt source for the second priority queue is not > connected, they work in polling mode only. This change connects the > second interrupt source for platforms where it is available. This patch > has been tested using the lwIP stack with a Xilinx-supplied driver from > their embeddedsw repository. > > Signed-off-by: Kinsey Moore <kinsey.moore@oarcorp.com> > --- > hw/arm/xlnx-versal.c | 1 + > hw/arm/xlnx-zynqmp.c | 2 ++ > 2 files changed, 3 insertions(+) > > diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c > index 60bf5fe657..a9e06b7fd1 100644 > --- a/hw/arm/xlnx-versal.c > +++ b/hw/arm/xlnx-versal.c > @@ -272,6 +272,7 @@ static void versal_create_gems(Versal *s, qemu_irq *pic) > memory_region_add_subregion(&s->mr_ps, addrs[i], mr); > > sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]); > + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[irqs[i]]); This is correct (thanks!) but the lines need to be connected through a qemu_or_irq (in both places), you can look into this commit: c74ccb5dd6 for an example (and reason). Best regards, Francisco > g_free(name); > } > } > diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c > index 5905a33015..b919b38e91 100644 > --- a/hw/arm/xlnx-zynqmp.c > +++ b/hw/arm/xlnx-zynqmp.c > @@ -635,6 +635,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) > sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); > sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, > gic_spi[gem_intr[i]]); > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 1, > + gic_spi[gem_intr[i]]); > } > > for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { > -- > 2.30.2 > > ^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH] hw/arm/xlnx: Connect secondary CGEM IRQs 2023-06-16 8:27 ` Francisco Iglesias @ 2023-06-16 14:08 ` Kinsey Moore 0 siblings, 0 replies; 4+ messages in thread From: Kinsey Moore @ 2023-06-16 14:08 UTC (permalink / raw) To: Francisco Iglesias; +Cc: qemu-devel@nongnu.org Thanks for the review. I'll get this updated and sent back out as soon as I've tested it. Kinsey -----Original Message----- From: Francisco Iglesias <frasse.iglesias@gmail.com> Sent: Friday, June 16, 2023 3:28 AM To: Kinsey Moore <kinsey.moore@oarcorp.com> Cc: qemu-devel@nongnu.org Subject: Re: [PATCH] hw/arm/xlnx: Connect secondary CGEM IRQs Hi Kinsey, On [2023 Jun 15] Thu 08:48:47, Kinsey Moore wrote: > The Cadence GEM peripherals as configured for Zynq MPSoC and Versal > platforms have two priority queues with separate interrupt sources for > each. If the interrupt source for the second priority queue is not > connected, they work in polling mode only. This change connects the > second interrupt source for platforms where it is available. This patch > has been tested using the lwIP stack with a Xilinx-supplied driver from > their embeddedsw repository. > > Signed-off-by: Kinsey Moore <kinsey.moore@oarcorp.com> > --- > hw/arm/xlnx-versal.c | 1 + > hw/arm/xlnx-zynqmp.c | 2 ++ > 2 files changed, 3 insertions(+) > > diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c > index 60bf5fe657..a9e06b7fd1 100644 > --- a/hw/arm/xlnx-versal.c > +++ b/hw/arm/xlnx-versal.c > @@ -272,6 +272,7 @@ static void versal_create_gems(Versal *s, qemu_irq *pic) > memory_region_add_subregion(&s->mr_ps, addrs[i], mr); > > sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]); > + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[irqs[i]]); This is correct (thanks!) but the lines need to be connected through a qemu_or_irq (in both places), you can look into this commit: c74ccb5dd6 for an example (and reason). Best regards, Francisco > g_free(name); > } > } > diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c > index 5905a33015..b919b38e91 100644 > --- a/hw/arm/xlnx-zynqmp.c > +++ b/hw/arm/xlnx-zynqmp.c > @@ -635,6 +635,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) > sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); > sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, > gic_spi[gem_intr[i]]); > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 1, > + gic_spi[gem_intr[i]]); > } > > for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { > -- > 2.30.2 > > ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-06-16 14:14 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-06-15 13:48 [PATCH 0/1] Secondary Cadence GEM IRQs Kinsey Moore 2023-06-15 13:48 ` [PATCH] hw/arm/xlnx: Connect secondary CGEM IRQs Kinsey Moore 2023-06-16 8:27 ` Francisco Iglesias 2023-06-16 14:08 ` Kinsey Moore
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