From: Andrew Jones <ajones@ventanamicro.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org,
liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com,
palmer@rivosinc.com
Subject: Re: [PATCH v2 14/18] target/riscv/kvm.c: add multi-letter extension KVM properties
Date: Mon, 19 Jun 2023 11:44:04 +0200 [thread overview]
Message-ID: <20230619-b52d0e7dff9ed47827902b54@orel> (raw)
In-Reply-To: <20230613205857.495165-15-dbarboza@ventanamicro.com>
On Tue, Jun 13, 2023 at 05:58:53PM -0300, Daniel Henrique Barboza wrote:
> Let's add KVM user properties for the multi-letter extensions that KVM
> currently supports: zicbom, zicboz, zihintpause, zbb, ssaia, sstc,
> svinval and svpbmt.
>
> As with MISA extensions, we're using the KVMCPUConfig type to hold
> information about the state of each extension. However, multi-letter
> extensions have more cases to cover than MISA extensions, so we're
> adding an extra 'supported' flag as well. This flag will reflect if a
> given extension is supported by KVM, i.e. KVM knows how to handle it.
> This is determined during KVM extension discovery in
> kvm_riscv_init_multiext_cfg(), where we test for EINVAL errors. Any
> other error different from EINVAL will cause an abort.
>
> The use of the 'user_set' is similar to what we already do with MISA
> extensions: the flag set only if the user is changing the extension
> state.
>
> The 'supported' flag will be used later on to make an exception for
> users that are disabling multi-letter extensions that are unknown to
> KVM.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/kvm.c | 124 +++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 124 insertions(+)
>
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
> index ea38f91b92..63bf97fbff 100644
> --- a/target/riscv/kvm.c
> +++ b/target/riscv/kvm.c
> @@ -113,6 +113,7 @@ typedef struct KVMCPUConfig {
> target_ulong offset;
> int kvm_reg_id;
> bool user_set;
> + bool supported;
> } KVMCPUConfig;
>
> #define KVM_MISA_CFG(_bit, _reg_id) \
> @@ -199,6 +200,86 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs)
> }
> }
>
> +#define CPUCFG(_prop) offsetof(struct RISCVCPUConfig, _prop)
> +
> +#define KVM_EXT_CFG(_name, _prop, _reg_id) \
> + {.name = _name, .offset = CPUCFG(_prop), \
> + .kvm_reg_id = _reg_id}
> +/*
> + * KVM ISA Multi-letter extensions. We care about the order
> + * since it'll be used to create the ISA string later on.
> + * We follow the same ordering rules of isa_edata_arr[]
> + * from target/riscv/cpu.c.
> + */
> +static KVMCPUConfig kvm_multi_ext_cfgs[] = {
> + KVM_EXT_CFG("zicbom", ext_icbom, KVM_RISCV_ISA_EXT_ZICBOM),
> + KVM_EXT_CFG("zicboz", ext_icboz, KVM_RISCV_ISA_EXT_ZICBOZ),
> + KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE),
> + KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB),
> + KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA),
> + KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC),
> + KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL),
> + KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT),
> +};
> +
> +static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext,
> + uint32_t val)
> +{
> + int cpu_cfg_offset = multi_ext->offset;
> + bool *ext_enabled = (void *)&cpu->cfg + cpu_cfg_offset;
> +
> + *ext_enabled = val;
> +}
> +
> +static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu,
> + KVMCPUConfig *multi_ext)
> +{
> + int cpu_cfg_offset = multi_ext->offset;
> + bool *ext_enabled = (void *)&cpu->cfg + cpu_cfg_offset;
> +
> + return *ext_enabled;
> +}
> +
> +static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v,
> + const char *name,
> + void *opaque, Error **errp)
> +{
> + KVMCPUConfig *multi_ext_cfg = opaque;
> + RISCVCPU *cpu = RISCV_CPU(obj);
> + bool value, host_val;
> +
> + if (!visit_type_bool(v, name, &value, errp)) {
> + return;
> + }
> +
> + host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
> +
> + /*
> + * Ignore if the user is setting the same value
> + * as the host.
> + */
> + if (value == host_val) {
> + return;
> + }
> +
> + if (!multi_ext_cfg->supported) {
> + /*
> + * Error out if the user is trying to enable an
> + * extension that KVM doesn't support. Ignore
> + * option otherwise.
> + */
> + if (value) {
> + error_setg(errp, "KVM does not support disabling extension %s",
> + multi_ext_cfg->name);
> + }
> +
> + return;
> + }
> +
> + multi_ext_cfg->user_set = true;
> + kvm_cpu_cfg_set(cpu, multi_ext_cfg, value);
> +}
> +
> static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
> {
> int i;
> @@ -213,6 +294,15 @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
> object_property_set_description(cpu_obj, misa_cfg->name,
> misa_cfg->description);
> }
> +
> + for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) {
> + KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i];
> +
> + object_property_add(cpu_obj, multi_cfg->name, "bool",
> + NULL,
> + kvm_cpu_set_multi_ext_cfg,
> + NULL, multi_cfg);
> + }
> }
>
> static int kvm_riscv_get_regs_core(CPUState *cs)
> @@ -528,6 +618,39 @@ static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu,
> env->misa_ext = env->misa_ext_mask;
> }
>
> +static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
> +{
> + CPURISCVState *env = &cpu->env;
> + uint64_t val;
> + int i, ret;
> +
> + for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) {
> + KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i];
> + struct kvm_one_reg reg;
> +
> + reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT,
> + multi_ext_cfg->kvm_reg_id);
> + reg.addr = (uint64_t)&val;
> + ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®);
> + if (ret != 0) {
> + if (ret == -EINVAL) {
> + /* Silently default to 'false' if KVM does not support it. */
> + multi_ext_cfg->supported = false;
> + val = false;
> + } else {
> + error_report("Unable to read ISA_EXT KVM register %s, "
> + "error %d", multi_ext_cfg->name, ret);
> + kvm_riscv_destroy_scratch_vcpu(kvmcpu);
> + exit(EXIT_FAILURE);
> + }
> + } else {
> + multi_ext_cfg->supported = true;
> + }
> +
> + kvm_cpu_cfg_set(cpu, multi_ext_cfg, val);
> + }
> +}
> +
> void kvm_riscv_init_user_properties(Object *cpu_obj)
> {
> RISCVCPU *cpu = RISCV_CPU(cpu_obj);
> @@ -540,6 +663,7 @@ void kvm_riscv_init_user_properties(Object *cpu_obj)
> kvm_riscv_add_cpu_user_properties(cpu_obj);
> kvm_riscv_init_machine_ids(cpu, &kvmcpu);
> kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu);
> + kvm_riscv_init_multiext_cfg(cpu, &kvmcpu);
>
> kvm_riscv_destroy_scratch_vcpu(&kvmcpu);
> }
> --
> 2.40.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
next prev parent reply other threads:[~2023-06-19 9:44 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-13 20:58 [PATCH v2 00/18] target/riscv, KVM: fixes and enhancements Daniel Henrique Barboza
2023-06-13 20:58 ` [PATCH v2 01/18] target/riscv: skip features setup for KVM CPUs Daniel Henrique Barboza
2023-06-13 20:58 ` [PATCH v2 02/18] hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set Daniel Henrique Barboza
2023-06-13 20:58 ` [PATCH v2 03/18] target/riscv/cpu.c: restrict 'mvendorid' value Daniel Henrique Barboza
2023-06-22 1:07 ` Alistair Francis
2023-06-13 20:58 ` [PATCH v2 04/18] target/riscv/cpu.c: restrict 'mimpid' value Daniel Henrique Barboza
2023-06-22 1:08 ` Alistair Francis
2023-06-13 20:58 ` [PATCH v2 05/18] target/riscv/cpu.c: restrict 'marchid' value Daniel Henrique Barboza
2023-06-22 1:10 ` Alistair Francis
2023-06-13 20:58 ` [PATCH v2 06/18] target/riscv: use KVM scratch CPUs to init KVM properties Daniel Henrique Barboza
2023-06-13 20:58 ` [PATCH v2 07/18] target/riscv: read marchid/mimpid in kvm_riscv_init_machine_ids() Daniel Henrique Barboza
2023-06-13 20:58 ` [PATCH v2 08/18] target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs Daniel Henrique Barboza
2023-06-22 1:16 ` Alistair Francis
2023-06-13 20:58 ` [PATCH v2 09/18] linux-headers: Update to v6.4-rc1 Daniel Henrique Barboza
2023-06-22 1:18 ` Alistair Francis
2023-06-13 20:58 ` [PATCH v2 10/18] target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPU Daniel Henrique Barboza
2023-06-22 1:34 ` Alistair Francis
2023-06-13 20:58 ` [PATCH v2 11/18] target/riscv/cpu: add misa_ext_infos[] Daniel Henrique Barboza
2023-06-19 9:05 ` Andrew Jones
2023-06-13 20:58 ` [PATCH v2 12/18] target/riscv: add KVM specific MISA properties Daniel Henrique Barboza
2023-06-19 9:17 ` Andrew Jones
2023-06-13 20:58 ` [PATCH v2 13/18] target/riscv/kvm.c: update KVM MISA bits Daniel Henrique Barboza
2023-06-19 9:30 ` Andrew Jones
2023-06-13 20:58 ` [PATCH v2 14/18] target/riscv/kvm.c: add multi-letter extension KVM properties Daniel Henrique Barboza
2023-06-19 9:44 ` Andrew Jones [this message]
2023-06-13 20:58 ` [PATCH v2 15/18] target/riscv: make riscv_isa_string_ext() KVM compatible Daniel Henrique Barboza
2023-06-19 9:54 ` Andrew Jones
2023-06-20 22:05 ` Daniel Henrique Barboza
2023-06-21 8:20 ` Andrew Jones
2023-06-21 9:13 ` Andrew Jones
2023-06-21 9:43 ` Daniel Henrique Barboza
2023-06-13 20:58 ` [PATCH v2 16/18] target/riscv: update multi-letter extension KVM properties Daniel Henrique Barboza
2023-06-13 20:58 ` [PATCH v2 17/18] target/riscv/kvm.c: add kvmconfig_get_cfg_addr() helper Daniel Henrique Barboza
2023-06-19 9:55 ` Andrew Jones
2023-06-13 20:58 ` [PATCH v2 18/18] target/riscv/kvm.c: read/write (cbom|cboz)_blocksize in KVM Daniel Henrique Barboza
2023-06-19 12:33 ` Andrew Jones
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