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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, Peter Maydell <peter.maydell@linaro.org>
Subject: [PATCH v5 14/20] target/arm: Use get_phys_addr_with_struct in S1_ptw_translate
Date: Tue, 20 Jun 2023 14:44:12 +0200	[thread overview]
Message-ID: <20230620124418.805717-15-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230620124418.805717-1-richard.henderson@linaro.org>

Do not provide a fast-path for physical addresses,
as those will need to be validated for GPC.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/ptw.c | 44 +++++++++++++++++---------------------------
 1 file changed, 17 insertions(+), 27 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 45271d666b..6d5e4855a3 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -264,37 +264,27 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
          * From gdbstub, do not use softmmu so that we don't modify the
          * state of the cpu at all, including softmmu tlb contents.
          */
-        if (regime_is_stage2(s2_mmu_idx)) {
-            S1Translate s2ptw = {
-                .in_mmu_idx = s2_mmu_idx,
-                .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx),
-                .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S,
-                .in_space = (s2_mmu_idx == ARMMMUIdx_Stage2_S ? ARMSS_Secure
-                             : space == ARMSS_Realm ? ARMSS_Realm
-                             : ARMSS_NonSecure),
-                .in_debug = true,
-            };
-            GetPhysAddrResult s2 = { };
+        S1Translate s2ptw = {
+            .in_mmu_idx = s2_mmu_idx,
+            .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx),
+            .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S,
+            .in_space = (s2_mmu_idx == ARMMMUIdx_Stage2_S ? ARMSS_Secure
+                         : space == ARMSS_Realm ? ARMSS_Realm
+                         : ARMSS_NonSecure),
+            .in_debug = true,
+        };
+        GetPhysAddrResult s2 = { };
 
-            if (get_phys_addr_lpae(env, &s2ptw, addr, MMU_DATA_LOAD,
-                                   false, &s2, fi)) {
-                goto fail;
-            }
-            ptw->out_phys = s2.f.phys_addr;
-            pte_attrs = s2.cacheattrs.attrs;
-            ptw->out_secure = s2.f.attrs.secure;
-            ptw->out_space = s2.f.attrs.space;
-        } else {
-            /* Regime is physical. */
-            ptw->out_phys = addr;
-            pte_attrs = 0;
-            ptw->out_secure = s2_mmu_idx == ARMMMUIdx_Phys_S;
-            ptw->out_space = (s2_mmu_idx == ARMMMUIdx_Phys_S ? ARMSS_Secure
-                              : space == ARMSS_Realm ? ARMSS_Realm
-                              : ARMSS_NonSecure);
+        if (get_phys_addr_with_struct(env, &s2ptw, addr,
+                                      MMU_DATA_LOAD, &s2, fi)) {
+            goto fail;
         }
+        ptw->out_phys = s2.f.phys_addr;
+        pte_attrs = s2.cacheattrs.attrs;
         ptw->out_host = NULL;
         ptw->out_rw = false;
+        ptw->out_secure = s2.f.attrs.secure;
+        ptw->out_space = s2.f.attrs.space;
     } else {
 #ifdef CONFIG_TCG
         CPUTLBEntryFull *full;
-- 
2.34.1



  parent reply	other threads:[~2023-06-20 12:46 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-20 12:43 [PATCH v5 00/20] target/arm: Implement FEAT_RME Richard Henderson
2023-06-20 12:43 ` [PATCH v5 01/20] target/arm: Add isar_feature_aa64_rme Richard Henderson
2023-06-20 12:44 ` [PATCH v5 02/20] target/arm: Update SCR and HCR for RME Richard Henderson
2023-06-20 12:44 ` [PATCH v5 03/20] target/arm: SCR_EL3.NS may be RES1 Richard Henderson
2023-06-20 12:44 ` [PATCH v5 04/20] target/arm: Add RME cpregs Richard Henderson
2023-06-20 12:44 ` [PATCH v5 05/20] target/arm: Introduce ARMSecuritySpace Richard Henderson
2023-06-20 12:44 ` [PATCH v5 06/20] include/exec/memattrs: Add two bits of space to MemTxAttrs Richard Henderson
2023-06-20 12:44 ` [PATCH v5 07/20] target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx Richard Henderson
2023-06-20 12:44 ` [PATCH v5 08/20] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root} Richard Henderson
2023-06-20 12:44 ` [PATCH v5 09/20] target/arm: Remove __attribute__((nonnull)) from ptw.c Richard Henderson
2023-06-20 12:44 ` [PATCH v5 10/20] target/arm: Pipe ARMSecuritySpace through ptw.c Richard Henderson
2023-06-20 12:44 ` [PATCH v5 11/20] target/arm: NSTable is RES0 for the RME EL3 regime Richard Henderson
2023-06-20 12:44 ` [PATCH v5 12/20] target/arm: Handle Block and Page bits for security space Richard Henderson
2023-06-20 12:44 ` [PATCH v5 13/20] target/arm: Handle no-execute for Realm and Root regimes Richard Henderson
2023-06-20 12:44 ` Richard Henderson [this message]
2023-06-20 12:44 ` [PATCH v5 15/20] target/arm: Move s1_is_el0 into S1Translate Richard Henderson
2023-06-20 12:44 ` [PATCH v5 16/20] target/arm: Use get_phys_addr_with_struct for stage2 Richard Henderson
2023-06-20 12:44 ` [PATCH v5 17/20] target/arm: Add GPC syndrome Richard Henderson
2023-06-20 12:44 ` [PATCH v5 18/20] target/arm: Implement GPC exceptions Richard Henderson
2023-06-20 12:44 ` [PATCH v5 19/20] target/arm: Implement the granule protection check Richard Henderson
2023-06-20 12:44 ` [PATCH v5 20/20] target/arm: Add cpu properties for enabling FEAT_RME Richard Henderson
2023-06-20 13:52   ` Peter Maydell
2023-06-20 14:03     ` Richard Henderson
2023-06-20 15:57 ` [PATCH v5 00/20] target/arm: Implement FEAT_RME Peter Maydell
2023-06-20 16:28   ` Richard Henderson
2023-06-20 16:41     ` Peter Maydell
2023-06-22 12:45 ` Peter Maydell

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