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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH v5 20/20] target/arm: Add cpu properties for enabling FEAT_RME
Date: Tue, 20 Jun 2023 14:44:18 +0200	[thread overview]
Message-ID: <20230620124418.805717-21-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230620124418.805717-1-richard.henderson@linaro.org>

Add an x-rme cpu property to enable FEAT_RME.
Add an x-l0gptsz property to set GPCCR_EL3.L0GPTSZ,
for testing various possible configurations.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/tcg/cpu64.c | 53 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 2976f94ae4..6fec2d8a57 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -142,6 +142,56 @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
     cpu->sve_max_vq = max_vq;
 }
 
+static bool cpu_arm_get_rme(Object *obj, Error **errp)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+    return cpu_isar_feature(aa64_rme, cpu);
+}
+
+static void cpu_arm_set_rme(Object *obj, bool value, Error **errp)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+    uint64_t t;
+
+    t = cpu->isar.id_aa64pfr0;
+    t = FIELD_DP64(t, ID_AA64PFR0, RME, value);
+    cpu->isar.id_aa64pfr0 = t;
+}
+
+static void cpu_max_set_l0gptsz(Object *obj, Visitor *v, const char *name,
+                                void *opaque, Error **errp)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+    uint32_t value;
+
+    if (!visit_type_uint32(v, name, &value, errp)) {
+        return;
+    }
+
+    /* Encode the value for the GPCCR_EL3 field. */
+    switch (value) {
+    case 30:
+    case 34:
+    case 36:
+    case 39:
+        cpu->reset_l0gptsz = value - 30;
+        break;
+    default:
+        error_setg(errp, "invalid value for l0gptsz");
+        error_append_hint(errp, "valid values are 30, 34, 36, 39\n");
+        break;
+    }
+}
+
+static void cpu_max_get_l0gptsz(Object *obj, Visitor *v, const char *name,
+                                void *opaque, Error **errp)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+    uint32_t value = cpu->reset_l0gptsz + 30;
+
+    visit_type_uint32(v, name, &value, errp);
+}
+
 static Property arm_cpu_lpa2_property =
     DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true);
 
@@ -700,6 +750,9 @@ void aarch64_max_tcg_initfn(Object *obj)
     aarch64_add_sme_properties(obj);
     object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
                         cpu_max_set_sve_max_vq, NULL, NULL);
+    object_property_add_bool(obj, "x-rme", cpu_arm_get_rme, cpu_arm_set_rme);
+    object_property_add(obj, "x-l0gptsz", "uint32", cpu_max_get_l0gptsz,
+                        cpu_max_set_l0gptsz, NULL, NULL);
     qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);
 }
 
-- 
2.34.1



  parent reply	other threads:[~2023-06-20 12:49 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-20 12:43 [PATCH v5 00/20] target/arm: Implement FEAT_RME Richard Henderson
2023-06-20 12:43 ` [PATCH v5 01/20] target/arm: Add isar_feature_aa64_rme Richard Henderson
2023-06-20 12:44 ` [PATCH v5 02/20] target/arm: Update SCR and HCR for RME Richard Henderson
2023-06-20 12:44 ` [PATCH v5 03/20] target/arm: SCR_EL3.NS may be RES1 Richard Henderson
2023-06-20 12:44 ` [PATCH v5 04/20] target/arm: Add RME cpregs Richard Henderson
2023-06-20 12:44 ` [PATCH v5 05/20] target/arm: Introduce ARMSecuritySpace Richard Henderson
2023-06-20 12:44 ` [PATCH v5 06/20] include/exec/memattrs: Add two bits of space to MemTxAttrs Richard Henderson
2023-06-20 12:44 ` [PATCH v5 07/20] target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx Richard Henderson
2023-06-20 12:44 ` [PATCH v5 08/20] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root} Richard Henderson
2023-06-20 12:44 ` [PATCH v5 09/20] target/arm: Remove __attribute__((nonnull)) from ptw.c Richard Henderson
2023-06-20 12:44 ` [PATCH v5 10/20] target/arm: Pipe ARMSecuritySpace through ptw.c Richard Henderson
2023-06-20 12:44 ` [PATCH v5 11/20] target/arm: NSTable is RES0 for the RME EL3 regime Richard Henderson
2023-06-20 12:44 ` [PATCH v5 12/20] target/arm: Handle Block and Page bits for security space Richard Henderson
2023-06-20 12:44 ` [PATCH v5 13/20] target/arm: Handle no-execute for Realm and Root regimes Richard Henderson
2023-06-20 12:44 ` [PATCH v5 14/20] target/arm: Use get_phys_addr_with_struct in S1_ptw_translate Richard Henderson
2023-06-20 12:44 ` [PATCH v5 15/20] target/arm: Move s1_is_el0 into S1Translate Richard Henderson
2023-06-20 12:44 ` [PATCH v5 16/20] target/arm: Use get_phys_addr_with_struct for stage2 Richard Henderson
2023-06-20 12:44 ` [PATCH v5 17/20] target/arm: Add GPC syndrome Richard Henderson
2023-06-20 12:44 ` [PATCH v5 18/20] target/arm: Implement GPC exceptions Richard Henderson
2023-06-20 12:44 ` [PATCH v5 19/20] target/arm: Implement the granule protection check Richard Henderson
2023-06-20 12:44 ` Richard Henderson [this message]
2023-06-20 13:52   ` [PATCH v5 20/20] target/arm: Add cpu properties for enabling FEAT_RME Peter Maydell
2023-06-20 14:03     ` Richard Henderson
2023-06-20 15:57 ` [PATCH v5 00/20] target/arm: Implement FEAT_RME Peter Maydell
2023-06-20 16:28   ` Richard Henderson
2023-06-20 16:41     ` Peter Maydell
2023-06-22 12:45 ` Peter Maydell

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