From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-ppc@nongnu.org
Cc: Nicholas Piggin <npiggin@gmail.com>,
qemu-devel@nongnu.org, Harsh Prateek Bora <harshpb@linux.ibm.com>,
Daniel Henrique Barboza <danielhb413@gmail.com>,
Anushree Mathur <anushree.mathur@linux.vnet.ibm.com>
Subject: [PATCH 2/4] target/ppc: Change partition-scope translate interface
Date: Tue, 20 Jun 2023 23:10:42 +1000 [thread overview]
Message-ID: <20230620131044.169110-3-npiggin@gmail.com> (raw)
In-Reply-To: <20230620131044.169110-1-npiggin@gmail.com>
Rather than always performing partition scope page table translation
with access type of 0 (MMU_DATA_LOAD), pass through the processor
access type which first initiated the translation sequence. Process-
scoped page table loads are then set to MMU_DATA_LOAD access type in
the xlate function.
This will allow more information to be passed to the exception
handler in the next patch.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/mmu-radix64.c | 24 ++++++++++++++++--------
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index 031efda0df..1fc1ba3ecf 100644
--- a/target/ppc/mmu-radix64.c
+++ b/target/ppc/mmu-radix64.c
@@ -380,6 +380,14 @@ static int ppc_radix64_partition_scoped_xlate(PowerPCCPU *cpu,
hwaddr pte_addr;
uint64_t pte;
+ if (pde_addr) {
+ /*
+ * Translation of process-scoped tables/directories is performed as
+ * a read-access.
+ */
+ access_type = MMU_DATA_LOAD;
+ }
+
qemu_log_mask(CPU_LOG_MMU, "%s for %s @0x%"VADDR_PRIx
" mmu_idx %u 0x%"HWADDR_PRIx"\n",
__func__, access_str(access_type),
@@ -477,10 +485,10 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu,
* is only used to translate the effective addresses of the
* process table entries.
*/
- ret = ppc_radix64_partition_scoped_xlate(cpu, 0, eaddr, prtbe_addr,
- pate, &h_raddr, &h_prot,
- &h_page_size, true,
- /* mmu_idx is 5 because we're translating from hypervisor scope */
+ /* mmu_idx is 5 because we're translating from hypervisor scope */
+ ret = ppc_radix64_partition_scoped_xlate(cpu, access_type, eaddr,
+ prtbe_addr, pate, &h_raddr,
+ &h_prot, &h_page_size, true,
5, guest_visible);
if (ret) {
return ret;
@@ -519,11 +527,11 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu,
* translation
*/
do {
- ret = ppc_radix64_partition_scoped_xlate(cpu, 0, eaddr, pte_addr,
- pate, &h_raddr, &h_prot,
- &h_page_size, true,
/* mmu_idx is 5 because we're translating from hypervisor scope */
- 5, guest_visible);
+ ret = ppc_radix64_partition_scoped_xlate(cpu, access_type, eaddr,
+ pte_addr, pate, &h_raddr,
+ &h_prot, &h_page_size,
+ true, 5, guest_visible);
if (ret) {
return ret;
}
--
2.40.1
next prev parent reply other threads:[~2023-06-20 13:11 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-20 13:10 [PATCH 0/4] target/ppc: Fixes for instruction-related Nicholas Piggin
2023-06-20 13:10 ` [PATCH 1/4] target/ppc: Fix instruction loading endianness in alignment interrupt Nicholas Piggin
2023-06-20 14:26 ` BALATON Zoltan
2023-06-20 16:54 ` Nicholas Piggin
2023-06-21 5:41 ` Nicholas Piggin
2023-06-20 13:10 ` Nicholas Piggin [this message]
2023-06-20 13:10 ` [PATCH 3/4] target/ppc: Add SRR1 prefix indication to interrupt handlers Nicholas Piggin
2023-06-20 13:10 ` [PATCH 4/4] target/ppc: Implement HEIR SPR Nicholas Piggin
2023-06-23 9:31 ` [PATCH 0/4] target/ppc: Fixes for instruction-related Cédric Le Goater
2023-06-28 5:56 ` Anushree Mathur
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