From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-ppc@nongnu.org
Cc: Nicholas Piggin <npiggin@gmail.com>,
qemu-devel@nongnu.org, Harsh Prateek Bora <harshpb@linux.ibm.com>,
Daniel Henrique Barboza <danielhb413@gmail.com>
Subject: [PATCH] target/ppc: Add ISA v3.1 LEV indication in SRR1 for system call interrupts
Date: Tue, 20 Jun 2023 23:13:21 +1000 [thread overview]
Message-ID: <20230620131321.169261-1-npiggin@gmail.com> (raw)
System call interrupts in ISA v3.1 CPUs add a LEV indication in SRR1
that corresponds with the LEV field of the instruction that caused the
interrupt.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
This is unchanged, just taken out of the bigger series since it is
independent.
Thanks,
Nick
target/ppc/excp_helper.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 77bfc18734..c7550fea13 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1591,6 +1591,10 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
vhc->hypercall(cpu->vhyp, cpu);
return;
}
+ if (env->insns_flags2 & PPC2_ISA310) {
+ /* ISAv3.1 puts LEV into SRR1 */
+ msr |= lev << 20;
+ }
if (lev == 1) {
new_msr |= (target_ulong)MSR_HVB;
}
--
2.40.1
next reply other threads:[~2023-06-20 13:14 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-20 13:13 Nicholas Piggin [this message]
2023-06-21 8:31 ` [PATCH] target/ppc: Add ISA v3.1 LEV indication in SRR1 for system call interrupts Harsh Prateek Bora
2023-06-21 10:13 ` Nicholas Piggin
2023-06-23 9:32 ` Cédric Le Goater
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