From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Cc: kbastian@mail.uni-paderborn.de, richard.henderson@linaro.org
Subject: [PATCH v3 6/8] target/tricore: Implement privilege level for all insns
Date: Wed, 21 Jun 2023 12:19:48 +0200 [thread overview]
Message-ID: <20230621101950.1645420-7-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <20230621101950.1645420-1-kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 43 +++++++++++++++++++++++++++++---------
1 file changed, 33 insertions(+), 10 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 1a0c6d35d3..1d570b49ff 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -387,7 +387,7 @@ static inline void gen_mtcr(DisasContext *ctx, TCGv r1,
}
}
} else {
- /* generate privilege trap */
+ generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
}
}
@@ -3373,7 +3373,11 @@ static void decode_sc_opc(DisasContext *ctx, int op1)
tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
break;
case OPC1_16_SC_BISR:
- gen_helper_1arg(bisr, const16 & 0xff);
+ if (ctx->priv == TRICORE_PRIV_SM) {
+ gen_helper_1arg(bisr, const16 & 0xff);
+ } else {
+ generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
+ }
break;
case OPC1_16_SC_LD_A:
gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
@@ -5234,7 +5238,11 @@ static void decode_rc_serviceroutine(DisasContext *ctx)
switch (op2) {
case OPC2_32_RC_BISR:
- gen_helper_1arg(bisr, const9);
+ if (ctx->priv == TRICORE_PRIV_SM) {
+ gen_helper_1arg(bisr, const9);
+ } else {
+ generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
+ }
break;
case OPC2_32_RC_SYSCALL:
generate_trap(ctx, TRAPC_SYSCALL, const9 & 0xff);
@@ -7882,20 +7890,33 @@ static void decode_sys_interrupts(DisasContext *ctx)
/* raise EXCP_DEBUG */
break;
case OPC2_32_SYS_DISABLE:
- tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask);
+ if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) {
+ tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask);
+ } else {
+ generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
+ }
break;
case OPC2_32_SYS_DISABLE_D:
if (has_feature(ctx, TRICORE_FEATURE_16)) {
- tcg_gen_extract_tl(cpu_gpr_d[r1], cpu_ICR, ctx->icr_ie_offset, 1);
- tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask);
+ if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) {
+ tcg_gen_extract_tl(cpu_gpr_d[r1], cpu_ICR,
+ ctx->icr_ie_offset, 1);
+ tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask);
+ } else {
+ generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
+ }
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
case OPC2_32_SYS_DSYNC:
break;
case OPC2_32_SYS_ENABLE:
- tcg_gen_ori_tl(cpu_ICR, cpu_ICR, ctx->icr_ie_mask);
- ctx->base.is_jmp = DISAS_EXIT_UPDATE;
+ if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) {
+ tcg_gen_ori_tl(cpu_ICR, cpu_ICR, ctx->icr_ie_mask);
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
+ } else {
+ generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
+ }
break;
case OPC2_32_SYS_ISYNC:
break;
@@ -7923,7 +7944,7 @@ static void decode_sys_interrupts(DisasContext *ctx)
gen_set_label(l1);
ctx->base.is_jmp = DISAS_EXIT;
} else {
- /* generate privilege trap */
+ generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
}
break;
case OPC2_32_SYS_RSLCX:
@@ -7936,7 +7957,9 @@ static void decode_sys_interrupts(DisasContext *ctx)
if (has_feature(ctx, TRICORE_FEATURE_16)) {
if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) {
tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1);
- } /* else raise privilege trap */
+ } else {
+ generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
+ }
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
--
2.40.1
next prev parent reply other threads:[~2023-06-21 10:20 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-21 10:19 [PATCH v3 0/8] TriCore Privilege Levels Bastian Koppelmann
2023-06-21 10:19 ` [PATCH v3 1/8] target/tricore: Fix RR_JLI clobbering reg A[11] Bastian Koppelmann
2023-06-21 10:19 ` [PATCH v3 2/8] target/tricore: Introduce DISAS_TARGET_EXIT Bastian Koppelmann
2023-06-21 10:19 ` [PATCH v3 3/8] target/tricore: ENABLE exit to main-loop Bastian Koppelmann
2023-06-21 10:19 ` [PATCH v3 4/8] target/tricore: Indirect jump insns use tcg_gen_lookup_and_goto_ptr() Bastian Koppelmann
2023-06-21 11:05 ` Richard Henderson
2023-06-21 10:19 ` [PATCH v3 5/8] target/tricore: Introduce priv tb flag Bastian Koppelmann
2023-06-21 10:19 ` Bastian Koppelmann [this message]
2023-06-21 10:19 ` [PATCH v3 7/8] target/tricore: Honour privilege changes on PSW write Bastian Koppelmann
2023-06-21 10:19 ` [PATCH v3 8/8] target/tricore: Fix ICR.IE offset in RESTORE insn Bastian Koppelmann
2023-06-21 11:06 ` Richard Henderson
2023-06-21 14:19 ` Bastian Koppelmann
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230621101950.1645420-7-kbastian@mail.uni-paderborn.de \
--to=kbastian@mail.uni-paderborn.de \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).