From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH v2 3/9] accel/tcg: Renumber TLB_DISCARD_WRITE
Date: Wed, 21 Jun 2023 14:18:56 +0200 [thread overview]
Message-ID: <20230621121902.1392277-4-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230621121902.1392277-1-richard.henderson@linaro.org>
Move to fill a hole in the set of bits.
Reduce the total number of tlb bits by 1.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-all.h | 4 ++--
tcg/tcg-op-ldst.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index b5618613cc..8018ce783e 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -325,10 +325,10 @@ CPUArchState *cpu_copy(CPUArchState *env);
#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2))
/* Set if TLB entry is an IO callback. */
#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3))
+/* Set if TLB entry writes ignored. */
+#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 4))
/* Set if the slow path must be used; more flags in CPUTLBEntryFull. */
#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5))
-/* Set if TLB entry writes ignored. */
-#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 6))
/*
* Use this mask to check interception with an alignment mask
diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c
index a4f51bfb6e..0fcc1618e5 100644
--- a/tcg/tcg-op-ldst.c
+++ b/tcg/tcg-op-ldst.c
@@ -39,7 +39,7 @@ static void check_max_alignment(unsigned a_bits)
* The requested alignment cannot overlap the TLB flags.
* FIXME: Must keep the count up-to-date with "exec/cpu-all.h".
*/
- tcg_debug_assert(a_bits + 6 <= tcg_ctx->page_bits);
+ tcg_debug_assert(a_bits + 5 <= tcg_ctx->page_bits);
#endif
}
--
2.34.1
next prev parent reply other threads:[~2023-06-21 12:20 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-21 12:18 [PATCH v2 0/9] {tcg,aarch64}: Add TLB_CHECK_ALIGNED Richard Henderson
2023-06-21 12:18 ` [PATCH v2 1/9] accel/tcg: Store some tlb flags in CPUTLBEntryFull Richard Henderson
2023-06-22 9:58 ` Philippe Mathieu-Daudé
2023-06-22 16:05 ` Richard Henderson
2023-06-21 12:18 ` [PATCH v2 2/9] accel/tcg: Move TLB_WATCHPOINT to TLB_SLOW_FLAGS_MASK Richard Henderson
2023-06-22 9:11 ` Philippe Mathieu-Daudé
2023-06-21 12:18 ` Richard Henderson [this message]
2023-06-22 9:09 ` [PATCH v2 3/9] accel/tcg: Renumber TLB_DISCARD_WRITE Philippe Mathieu-Daudé
2023-06-21 12:18 ` [PATCH v2 4/9] target/arm: Support 32-byte alignment in pow2_align Richard Henderson
2023-06-22 10:03 ` Philippe Mathieu-Daudé
2023-06-21 12:18 ` [PATCH v2 5/9] exec/memattrs: Remove target_tlb_bit* Richard Henderson
2023-06-21 12:18 ` [PATCH v2 6/9] accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull Richard Henderson
2023-06-21 12:19 ` [PATCH v2 7/9] accel/tcg: Add TLB_CHECK_ALIGNED Richard Henderson
2023-06-22 10:01 ` Philippe Mathieu-Daudé
2023-06-21 12:19 ` [PATCH v2 8/9] target/arm: Do memory type alignment check when translation disabled Richard Henderson
2023-06-21 12:19 ` [PATCH v2 9/9] target/arm: Do memory type alignment check when translation enabled Richard Henderson
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