From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Cc: kbastian@mail.uni-paderborn.de,
Richard Henderson <richard.henderson@linaro.org>
Subject: [PULL 20/20] target/tricore: Fix ICR.IE offset in RESTORE insn
Date: Wed, 21 Jun 2023 18:14:22 +0200 [thread overview]
Message-ID: <20230621161422.1652151-21-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <20230621161422.1652151-1-kbastian@mail.uni-paderborn.de>
from ISA v1.6.1 onwards the bit position of ICR.IE changed.
ctx->icr_ie_offset contains the correct value for the ISA version used
by the vCPU. We also need to exit this tb here, as we might have enabled
interrupts.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230621142302.1648383-9-kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 9e408f44ec..2f32463d4d 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -7964,7 +7964,9 @@ static void decode_sys_interrupts(DisasContext *ctx)
case OPC2_32_SYS_RESTORE:
if (has_feature(ctx, TRICORE_FEATURE_16)) {
if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) {
- tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1);
+ tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1],
+ ctx->icr_ie_offset, 1);
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
} else {
generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
}
--
2.40.1
next prev parent reply other threads:[~2023-06-21 16:17 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-21 16:14 [PULL 00/20] tricore queue Bastian Koppelmann
2023-06-21 16:14 ` [PULL 01/20] target/tricore: Introduce ISA 1.6.2 feature Bastian Koppelmann
2023-06-21 16:14 ` [PULL 02/20] target/tricore: Add popcnt.w insn Bastian Koppelmann
2023-06-21 16:14 ` [PULL 03/20] target/tricore: Add LHA insn Bastian Koppelmann
2023-06-21 16:14 ` [PULL 04/20] target/tricore: Add crc32l.w insn Bastian Koppelmann
2023-06-21 16:14 ` [PULL 05/20] target/tricore: Add crc32.b insn Bastian Koppelmann
2023-06-21 16:14 ` [PULL 06/20] target/tricore: Add shuffle insn Bastian Koppelmann
2023-06-21 16:14 ` [PULL 07/20] target/tricore: Implement SYCSCALL insn Bastian Koppelmann
2023-06-21 16:14 ` [PULL 08/20] target/tricore: Add DISABLE insn variant Bastian Koppelmann
2023-06-21 16:14 ` [PULL 09/20] target/tricore: Fix out-of-bounds index in imask instruction Bastian Koppelmann
2023-06-22 7:43 ` Michael Tokarev
2023-06-22 14:51 ` Bastian Koppelmann
2023-06-23 6:54 ` Michael Tokarev
2023-06-23 9:51 ` Bastian Koppelmann
2023-06-23 10:29 ` Michael Tokarev
2023-06-23 11:09 ` Bastian Koppelmann
2023-06-21 16:14 ` [PULL 10/20] target/tricore: Correctly fix saving PSW.CDE to CSA on call Bastian Koppelmann
2023-06-21 16:14 ` [PULL 11/20] target/tricore: Add CHECK_REG_PAIR() for insn accessing 64 bit regs Bastian Koppelmann
2023-06-21 16:14 ` [PULL 12/20] target/tricore: Fix helper_ret() not correctly restoring PSW Bastian Koppelmann
2023-06-21 16:14 ` [PULL 13/20] target/tricore: Fix RR_JLI clobbering reg A[11] Bastian Koppelmann
2023-06-21 16:14 ` [PULL 14/20] target/tricore: Introduce DISAS_TARGET_EXIT Bastian Koppelmann
2023-06-21 16:14 ` [PULL 15/20] target/tricore: ENABLE exit to main-loop Bastian Koppelmann
2023-06-21 16:14 ` [PULL 16/20] target/tricore: Indirect jump insns use tcg_gen_lookup_and_goto_ptr() Bastian Koppelmann
2023-06-21 16:14 ` [PULL 17/20] target/tricore: Introduce priv tb flag Bastian Koppelmann
2023-06-21 16:14 ` [PULL 18/20] target/tricore: Implement privilege level for all insns Bastian Koppelmann
2023-06-21 16:14 ` [PULL 19/20] target/tricore: Honour privilege changes on PSW write Bastian Koppelmann
2023-06-21 16:14 ` Bastian Koppelmann [this message]
2023-06-21 20:43 ` [PULL 00/20] tricore queue Richard Henderson
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