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[213.175.37.10]) by smtp.gmail.com with ESMTPSA id n6-20020a7bcbc6000000b003f7e4d143cfsm6961114wmi.15.2023.06.22.00.35.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jun 2023 00:35:52 -0700 (PDT) Date: Thu, 22 Jun 2023 09:35:52 +0200 From: Igor Mammedov To: Joel Upham Cc: qemu-devel@nongnu.org, "Michael S. Tsirkin" , Ani Sinha , Marcel Apfelbaum Subject: Re: [PATCH v1 02/23] pc/q35: Apply PCI bus BSEL property for Xen PCI device hotplug Message-ID: <20230622093552.1c11a46a@imammedo.users.ipa.redhat.com> In-Reply-To: References: <20230621132757.2a951cdf@imammedo.users.ipa.redhat.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=170.10.133.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, 21 Jun 2023 13:24:42 -0400 Joel Upham wrote: > On Wed, Jun 21, 2023 at 7:28=E2=80=AFAM Igor Mammedov wrote: >=20 > > On Tue, 20 Jun 2023 13:24:36 -0400 > > Joel Upham wrote: > > =20 > > > On Q35 we still need to assign BSEL property to bus(es) for PCI device > > > add/hotplug to work. > > > Extend acpi_set_pci_info() function to support Q35 as well. This patc= h =20 > > adds new (trivial) =20 > > > function find_q35() which returns root PCIBus object on Q35, in a way > > > similar to what find_i440fx does. =20 > > > > I think patch is mostly obsolete, q35 ACPI PCI hotplug is supported in > > upstream QEMU. > > > > Also see comment below. > > > > I make use of the find_q35() function in later patches, but I agree now= a =20 > majority of this patch is a bit different. There is likely an existing alternative already. (probably introduced by AC= PI PIC hotplug for q35) >=20 > > > > > > Signed-off-by: Alexey Gerasimenko > > > Signed-off-by: Joel Upham > > > --- > > > hw/acpi/pcihp.c | 4 +++- > > > hw/pci-host/q35.c | 9 +++++++++ > > > include/hw/i386/pc.h | 3 +++ > > > 3 files changed, 15 insertions(+), 1 deletion(-) > > > > > > diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c > > > index cdd6f775a1..f4e39d7a9c 100644 > > > --- a/hw/acpi/pcihp.c > > > +++ b/hw/acpi/pcihp.c > > > @@ -40,6 +40,7 @@ > > > #include "qapi/error.h" > > > #include "qom/qom-qobject.h" > > > #include "trace.h" > > > +#include "sysemu/xen.h" > > > > > > #define ACPI_PCIHP_SIZE 0x0018 > > > #define PCI_UP_BASE 0x0000 > > > @@ -84,7 +85,8 @@ static void *acpi_set_bsel(PCIBus *bus, void *opaqu= e) > > > bool is_bridge =3D IS_PCI_BRIDGE(br); > > > > > > /* hotplugged bridges can't be described in ACPI ignore them */ > > > - if (qbus_is_hotpluggable(BUS(bus))) { =20 > > =20 > > > + /* Xen requires hotplugging to the root device, even on the Q35 = =20 > > chipset */ > > pls explain what 'root device' is. > > Why can't you use root-ports for hotplug? > > > > Wording may have been incorrect. Root port is correct. This may not be= =20 > needed anymore, > and may have been left over for when I was debugging PCIe hotplugging > problems. > I will retest and fix patch once I know more. Xen expects the PCIe device > to be on the root port. >=20 > I can move the function to a different patch that uses it. >=20 > > > + if (qbus_is_hotpluggable(BUS(bus)) || xen_enabled()) { > > > if (!is_bridge || (!br->hotplugged && =20 > > info->has_bridge_hotplug)) { =20 > > > bus_bsel =3D g_malloc(sizeof *bus_bsel); > > > > > > diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c > > > index fd18920e7f..fe5fc0f47c 100644 > > > --- a/hw/pci-host/q35.c > > > +++ b/hw/pci-host/q35.c > > > @@ -259,6 +259,15 @@ static void q35_host_initfn(Object *obj) > > > qdev_prop_allow_set_link_before_realize= , =20 > > 0); =20 > > > } > > > > > > +PCIBus *find_q35(void) > > > +{ > > > + PCIHostState *s =3D OBJECT_CHECK(PCIHostState, > > > + object_resolve_path("/machine/q35= ", =20 > > NULL), =20 > > > + TYPE_PCI_HOST_BRIDGE); > > > + return s ? s->bus : NULL; > > > +} > > > + > > > + > > > static const TypeInfo q35_host_info =3D { > > > .name =3D TYPE_Q35_HOST_DEVICE, > > > .parent =3D TYPE_PCIE_HOST_BRIDGE, > > > diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h > > > index c661e9cc80..550f8fa221 100644 > > > --- a/include/hw/i386/pc.h > > > +++ b/include/hw/i386/pc.h > > > @@ -196,6 +196,9 @@ void pc_madt_cpu_entry(int uid, const CPUArchIdLi= st =20 > > *apic_ids, =20 > > > /* sgx.c */ > > > void pc_machine_init_sgx_epc(PCMachineState *pcms); > > > > > > +/* q35.c */ > > > +PCIBus *find_q35(void); > > > + > > > extern GlobalProperty pc_compat_8_0[]; > > > extern const size_t pc_compat_8_0_len; > > > =20 > > > > =20