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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id s13-20020a170906454d00b00988f168811bsm5716198ejq.135.2023.06.23.02.38.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jun 2023 02:38:32 -0700 (PDT) Date: Fri, 23 Jun 2023 11:38:31 +0200 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH v3 12/19] target/riscv: add KVM specific MISA properties Message-ID: <20230623-df5c527b7dae3e28123be577@orel> References: <20230622135700.105383-1-dbarboza@ventanamicro.com> <20230622135700.105383-13-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230622135700.105383-13-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=ajones@ventanamicro.com; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Jun 22, 2023 at 10:56:53AM -0300, Daniel Henrique Barboza wrote: ... > +#define KVM_MISA_CFG(_bit, _reg_id) \ > + {.offset = _bit, .kvm_reg_id = _reg_id} > + > +/* KVM ISA extensions */ > +static KVMCPUConfig kvm_misa_ext_cfgs[] = { > + KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), > + KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), > + KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), > + KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), > + KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), > + KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), > + KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), > +}; > + ... > +static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) > +{ > + int i; > + > + for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { > + KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; > + int bit = misa_cfg->offset; > + > + misa_cfg->name = misa_ext_info_arr[bit].name; > + misa_cfg->description = misa_ext_info_arr[bit].description; I'd prefer these be set by KVM_MISA_CFG(), since we can. No need to wait until runtime if we can do it at compile-time. Thanks, drew > + > + object_property_add(cpu_obj, misa_cfg->name, "bool", > + NULL, > + kvm_cpu_set_misa_ext_cfg, > + NULL, misa_cfg); > + object_property_set_description(cpu_obj, misa_cfg->name, > + misa_cfg->description); > + } > +} > + > static int kvm_riscv_get_regs_core(CPUState *cs) > { > int ret = 0; > @@ -427,6 +504,7 @@ void kvm_riscv_init_user_properties(Object *cpu_obj) > return; > } > > + kvm_riscv_add_cpu_user_properties(cpu_obj); > kvm_riscv_init_machine_ids(cpu, &kvmcpu); > kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); > > -- > 2.41.0 >