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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 21/26] docs/system/arm: Document FEAT_RME
Date: Fri, 23 Jun 2023 13:31:30 +0100	[thread overview]
Message-ID: <20230623123135.1788191-22-peter.maydell@linaro.org> (raw)
In-Reply-To: <20230623123135.1788191-1-peter.maydell@linaro.org>

From: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20230622143046.1578160-1-richard.henderson@linaro.org
[PMM: fixed typo; note experimental status in emulation.rst too]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/cpu-features.rst | 23 +++++++++++++++++++++++
 docs/system/arm/emulation.rst    |  1 +
 2 files changed, 24 insertions(+)

diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst
index f4524b6d3e7..6bb88a40c77 100644
--- a/docs/system/arm/cpu-features.rst
+++ b/docs/system/arm/cpu-features.rst
@@ -435,3 +435,26 @@ As with ``sve-default-vector-length``, if the default length is larger
 than the maximum vector length enabled, the actual vector length will
 be reduced.  If this property is set to ``-1`` then the default vector
 length is set to the maximum possible length.
+
+RME CPU Properties
+==================
+
+The status of RME support with QEMU is experimental.  At this time we
+only support RME within the CPU proper, not within the SMMU or GIC.
+The feature is enabled by the CPU property ``x-rme``, with the ``x-``
+prefix present as a reminder of the experimental status, and defaults off.
+
+The method for enabling RME will change in some future QEMU release
+without notice or backward compatibility.
+
+RME Level 0 GPT Size Property
+-----------------------------
+
+To aid firmware developers in testing different possible CPU
+configurations, ``x-l0gptsz=S`` may be used to specify the value
+to encode into ``GPCCR_EL3.L0GPTSZ``, a read-only field that
+specifies the size of the Level 0 Granule Protection Table.
+Legal values for ``S`` are 30, 34, 36, and 39; the default is 30.
+
+As with ``x-rme``, the ``x-l0gptsz`` property may be renamed or
+removed in some future QEMU release.
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index ecbbd63adf6..bdafc68819b 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -66,6 +66,7 @@ the following architecture extensions:
 - FEAT_RAS (Reliability, availability, and serviceability)
 - FEAT_RASv1p1 (RAS Extension v1.1)
 - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions)
+- FEAT_RME (Realm Management Extension) (NB: support status in QEMU is experimental)
 - FEAT_RNG (Random number generator)
 - FEAT_S2FWB (Stage 2 forced Write-Back)
 - FEAT_SB (Speculation Barrier)
-- 
2.34.1



  parent reply	other threads:[~2023-06-23 12:44 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-23 12:31 [PULL 00/26] target-arm queue Peter Maydell
2023-06-23 12:31 ` [PULL 01/26] target/arm: Add isar_feature_aa64_rme Peter Maydell
2023-06-23 12:31 ` [PULL 02/26] target/arm: Update SCR and HCR for RME Peter Maydell
2023-06-23 12:31 ` [PULL 03/26] target/arm: SCR_EL3.NS may be RES1 Peter Maydell
2023-06-23 12:31 ` [PULL 04/26] target/arm: Add RME cpregs Peter Maydell
2023-06-23 12:31 ` [PULL 05/26] target/arm: Introduce ARMSecuritySpace Peter Maydell
2023-06-23 12:31 ` [PULL 06/26] include/exec/memattrs: Add two bits of space to MemTxAttrs Peter Maydell
2023-06-23 12:31 ` [PULL 07/26] target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx Peter Maydell
2023-06-23 12:31 ` [PULL 08/26] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root} Peter Maydell
2023-06-23 12:31 ` [PULL 09/26] target/arm: Remove __attribute__((nonnull)) from ptw.c Peter Maydell
2023-06-23 12:31 ` [PULL 10/26] target/arm: Pipe ARMSecuritySpace through ptw.c Peter Maydell
2023-06-23 12:31 ` [PULL 11/26] target/arm: NSTable is RES0 for the RME EL3 regime Peter Maydell
2023-06-23 12:31 ` [PULL 12/26] target/arm: Handle Block and Page bits for security space Peter Maydell
2023-06-23 12:31 ` [PULL 13/26] target/arm: Handle no-execute for Realm and Root regimes Peter Maydell
2023-06-23 12:31 ` [PULL 14/26] target/arm: Use get_phys_addr_with_struct in S1_ptw_translate Peter Maydell
2023-06-23 12:31 ` [PULL 15/26] target/arm: Move s1_is_el0 into S1Translate Peter Maydell
2023-06-23 12:31 ` [PULL 16/26] target/arm: Use get_phys_addr_with_struct for stage2 Peter Maydell
2023-06-23 12:31 ` [PULL 17/26] target/arm: Add GPC syndrome Peter Maydell
2023-06-23 12:31 ` [PULL 18/26] target/arm: Implement GPC exceptions Peter Maydell
2023-06-23 12:31 ` [PULL 19/26] target/arm: Implement the granule protection check Peter Maydell
2023-06-23 12:31 ` [PULL 20/26] target/arm: Add cpu properties for enabling FEAT_RME Peter Maydell
2023-06-23 12:31 ` Peter Maydell [this message]
2023-06-23 12:31 ` [PULL 22/26] host-utils: Avoid using __builtin_subcll on buggy versions of Apple Clang Peter Maydell
2023-06-23 12:31 ` [PULL 23/26] target/arm: Restructure has_vfp_d32 test Peter Maydell
2023-06-23 12:31 ` [PULL 24/26] hw/arm/sbsa-ref: add ITS support in SBSA GIC Peter Maydell
2023-06-23 12:31 ` [PULL 25/26] target/arm: Fix sve predicate store, 8 <= VQ <= 15 Peter Maydell
2023-06-23 12:31 ` [PULL 26/26] pc-bios/keymaps: Use the official xkb name for Arabic layout, not the legacy synonym Peter Maydell
2023-06-25  8:25 ` [PULL 00/26] target-arm queue Richard Henderson

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