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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 23/26] target/arm: Restructure has_vfp_d32 test
Date: Fri, 23 Jun 2023 13:31:32 +0100	[thread overview]
Message-ID: <20230623123135.1788191-24-peter.maydell@linaro.org> (raw)
In-Reply-To: <20230623123135.1788191-1-peter.maydell@linaro.org>

From: Richard Henderson <richard.henderson@linaro.org>

One cannot test for feature aa32_simd_r32 without first
testing if AArch32 mode is supported at all.  This leads to

qemu-system-aarch64: ARM CPUs must have both VFP-D32 and Neon or neither

for Apple M1 cpus.

We already have a check for ARMv8-A never setting vfp-d32 true,
so restructure the code so that AArch64 avoids the test entirely.

Reported-by: Mads Ynddal <mads@ynddal.dk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Mads Ynddal <m.ynddal@samsung.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Mads Ynddal <m.ynddal@samsung.com>
Message-id: 20230619140216.402530-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 28 +++++++++++++++-------------
 1 file changed, 15 insertions(+), 13 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 842e1b53ee4..a1e77698ba2 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1402,25 +1402,27 @@ void arm_cpu_post_init(Object *obj)
      * KVM does not currently allow us to lie to the guest about its
      * ID/feature registers, so the guest always sees what the host has.
      */
-    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)
-        ? cpu_isar_feature(aa64_fp_simd, cpu)
-        : cpu_isar_feature(aa32_vfp, cpu)) {
-        cpu->has_vfp = true;
-        if (!kvm_enabled()) {
-            qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property);
+    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
+        if (cpu_isar_feature(aa64_fp_simd, cpu)) {
+            cpu->has_vfp = true;
+            cpu->has_vfp_d32 = true;
+            if (tcg_enabled() || qtest_enabled()) {
+                qdev_property_add_static(DEVICE(obj),
+                                         &arm_cpu_has_vfp_property);
+            }
         }
-    }
-
-    if (cpu->has_vfp && cpu_isar_feature(aa32_simd_r32, cpu)) {
-        cpu->has_vfp_d32 = true;
-        if (!kvm_enabled()) {
+    } else if (cpu_isar_feature(aa32_vfp, cpu)) {
+        cpu->has_vfp = true;
+        if (cpu_isar_feature(aa32_simd_r32, cpu)) {
+            cpu->has_vfp_d32 = true;
             /*
              * The permitted values of the SIMDReg bits [3:0] on
              * Armv8-A are either 0b0000 and 0b0010. On such CPUs,
              * make sure that has_vfp_d32 can not be set to false.
              */
-            if (!(arm_feature(&cpu->env, ARM_FEATURE_V8) &&
-                  !arm_feature(&cpu->env, ARM_FEATURE_M))) {
+            if ((tcg_enabled() || qtest_enabled())
+                && !(arm_feature(&cpu->env, ARM_FEATURE_V8)
+                     && !arm_feature(&cpu->env, ARM_FEATURE_M))) {
                 qdev_property_add_static(DEVICE(obj),
                                          &arm_cpu_has_vfp_d32_property);
             }
-- 
2.34.1



  parent reply	other threads:[~2023-06-23 12:32 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-23 12:31 [PULL 00/26] target-arm queue Peter Maydell
2023-06-23 12:31 ` [PULL 01/26] target/arm: Add isar_feature_aa64_rme Peter Maydell
2023-06-23 12:31 ` [PULL 02/26] target/arm: Update SCR and HCR for RME Peter Maydell
2023-06-23 12:31 ` [PULL 03/26] target/arm: SCR_EL3.NS may be RES1 Peter Maydell
2023-06-23 12:31 ` [PULL 04/26] target/arm: Add RME cpregs Peter Maydell
2023-06-23 12:31 ` [PULL 05/26] target/arm: Introduce ARMSecuritySpace Peter Maydell
2023-06-23 12:31 ` [PULL 06/26] include/exec/memattrs: Add two bits of space to MemTxAttrs Peter Maydell
2023-06-23 12:31 ` [PULL 07/26] target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx Peter Maydell
2023-06-23 12:31 ` [PULL 08/26] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root} Peter Maydell
2023-06-23 12:31 ` [PULL 09/26] target/arm: Remove __attribute__((nonnull)) from ptw.c Peter Maydell
2023-06-23 12:31 ` [PULL 10/26] target/arm: Pipe ARMSecuritySpace through ptw.c Peter Maydell
2023-06-23 12:31 ` [PULL 11/26] target/arm: NSTable is RES0 for the RME EL3 regime Peter Maydell
2023-06-23 12:31 ` [PULL 12/26] target/arm: Handle Block and Page bits for security space Peter Maydell
2023-06-23 12:31 ` [PULL 13/26] target/arm: Handle no-execute for Realm and Root regimes Peter Maydell
2023-06-23 12:31 ` [PULL 14/26] target/arm: Use get_phys_addr_with_struct in S1_ptw_translate Peter Maydell
2023-06-23 12:31 ` [PULL 15/26] target/arm: Move s1_is_el0 into S1Translate Peter Maydell
2023-06-23 12:31 ` [PULL 16/26] target/arm: Use get_phys_addr_with_struct for stage2 Peter Maydell
2023-06-23 12:31 ` [PULL 17/26] target/arm: Add GPC syndrome Peter Maydell
2023-06-23 12:31 ` [PULL 18/26] target/arm: Implement GPC exceptions Peter Maydell
2023-06-23 12:31 ` [PULL 19/26] target/arm: Implement the granule protection check Peter Maydell
2023-06-23 12:31 ` [PULL 20/26] target/arm: Add cpu properties for enabling FEAT_RME Peter Maydell
2023-06-23 12:31 ` [PULL 21/26] docs/system/arm: Document FEAT_RME Peter Maydell
2023-06-23 12:31 ` [PULL 22/26] host-utils: Avoid using __builtin_subcll on buggy versions of Apple Clang Peter Maydell
2023-06-23 12:31 ` Peter Maydell [this message]
2023-06-23 12:31 ` [PULL 24/26] hw/arm/sbsa-ref: add ITS support in SBSA GIC Peter Maydell
2023-06-23 12:31 ` [PULL 25/26] target/arm: Fix sve predicate store, 8 <= VQ <= 15 Peter Maydell
2023-06-23 12:31 ` [PULL 26/26] pc-bios/keymaps: Use the official xkb name for Arabic layout, not the legacy synonym Peter Maydell
2023-06-25  8:25 ` [PULL 00/26] target-arm queue Richard Henderson

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