From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 25/26] target/arm: Fix sve predicate store, 8 <= VQ <= 15
Date: Fri, 23 Jun 2023 13:31:34 +0100 [thread overview]
Message-ID: <20230623123135.1788191-26-peter.maydell@linaro.org> (raw)
In-Reply-To: <20230623123135.1788191-1-peter.maydell@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
Brown bag time: store instead of load results in uninitialized temp.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1704
Reported-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620134659.817559-1-richard.henderson@linaro.org
Fixes: e6dd5e782be ("target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r")
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/translate-sve.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index ff050626e66..225d358922c 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -4329,7 +4329,7 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs,
/* Predicate register stores can be any multiple of 2. */
if (len_remain >= 8) {
t0 = tcg_temp_new_i64();
- tcg_gen_st_i64(t0, base, vofs + len_align);
+ tcg_gen_ld_i64(t0, base, vofs + len_align);
tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ | MO_ATOM_NONE);
len_remain -= 8;
len_align += 8;
--
2.34.1
next prev parent reply other threads:[~2023-06-23 12:42 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-23 12:31 [PULL 00/26] target-arm queue Peter Maydell
2023-06-23 12:31 ` [PULL 01/26] target/arm: Add isar_feature_aa64_rme Peter Maydell
2023-06-23 12:31 ` [PULL 02/26] target/arm: Update SCR and HCR for RME Peter Maydell
2023-06-23 12:31 ` [PULL 03/26] target/arm: SCR_EL3.NS may be RES1 Peter Maydell
2023-06-23 12:31 ` [PULL 04/26] target/arm: Add RME cpregs Peter Maydell
2023-06-23 12:31 ` [PULL 05/26] target/arm: Introduce ARMSecuritySpace Peter Maydell
2023-06-23 12:31 ` [PULL 06/26] include/exec/memattrs: Add two bits of space to MemTxAttrs Peter Maydell
2023-06-23 12:31 ` [PULL 07/26] target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx Peter Maydell
2023-06-23 12:31 ` [PULL 08/26] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root} Peter Maydell
2023-06-23 12:31 ` [PULL 09/26] target/arm: Remove __attribute__((nonnull)) from ptw.c Peter Maydell
2023-06-23 12:31 ` [PULL 10/26] target/arm: Pipe ARMSecuritySpace through ptw.c Peter Maydell
2023-06-23 12:31 ` [PULL 11/26] target/arm: NSTable is RES0 for the RME EL3 regime Peter Maydell
2023-06-23 12:31 ` [PULL 12/26] target/arm: Handle Block and Page bits for security space Peter Maydell
2023-06-23 12:31 ` [PULL 13/26] target/arm: Handle no-execute for Realm and Root regimes Peter Maydell
2023-06-23 12:31 ` [PULL 14/26] target/arm: Use get_phys_addr_with_struct in S1_ptw_translate Peter Maydell
2023-06-23 12:31 ` [PULL 15/26] target/arm: Move s1_is_el0 into S1Translate Peter Maydell
2023-06-23 12:31 ` [PULL 16/26] target/arm: Use get_phys_addr_with_struct for stage2 Peter Maydell
2023-06-23 12:31 ` [PULL 17/26] target/arm: Add GPC syndrome Peter Maydell
2023-06-23 12:31 ` [PULL 18/26] target/arm: Implement GPC exceptions Peter Maydell
2023-06-23 12:31 ` [PULL 19/26] target/arm: Implement the granule protection check Peter Maydell
2023-06-23 12:31 ` [PULL 20/26] target/arm: Add cpu properties for enabling FEAT_RME Peter Maydell
2023-06-23 12:31 ` [PULL 21/26] docs/system/arm: Document FEAT_RME Peter Maydell
2023-06-23 12:31 ` [PULL 22/26] host-utils: Avoid using __builtin_subcll on buggy versions of Apple Clang Peter Maydell
2023-06-23 12:31 ` [PULL 23/26] target/arm: Restructure has_vfp_d32 test Peter Maydell
2023-06-23 12:31 ` [PULL 24/26] hw/arm/sbsa-ref: add ITS support in SBSA GIC Peter Maydell
2023-06-23 12:31 ` Peter Maydell [this message]
2023-06-23 12:31 ` [PULL 26/26] pc-bios/keymaps: Use the official xkb name for Arabic layout, not the legacy synonym Peter Maydell
2023-06-25 8:25 ` [PULL 00/26] target-arm queue Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230623123135.1788191-26-peter.maydell@linaro.org \
--to=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).