From: Igor Mammedov <imammedo@redhat.com>
To: Tao Su <tao1.su@linux.intel.com>
Cc: qemu-devel@nongnu.org, pbonzini@redhat.com, xiaoyao.li@intel.com,
lei4.wang@intel.com, qian.wen@intel.com
Subject: Re: [PATCH 3/7] target/i386: Allow MCDT_NO if host supports
Date: Mon, 26 Jun 2023 15:03:12 +0200 [thread overview]
Message-ID: <20230626150312.5edefe7b@imammedo.users.ipa.redhat.com> (raw)
In-Reply-To: <20230616032311.19137-4-tao1.su@linux.intel.com>
On Fri, 16 Jun 2023 11:23:07 +0800
Tao Su <tao1.su@linux.intel.com> wrote:
> MCDT_NO bit indicates HW contains the security fix and doesn't need to
> be mitigated to avoid data-dependent behaviour for certain instructions.
> It needs no hypervisor support. Treat it as supported regardless of what
> KVM reports.
>
> Signed-off-by: Tao Su <tao1.su@linux.intel.com>
> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
> ---
> target/i386/kvm/kvm.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
> index de531842f6..4defd8b479 100644
> --- a/target/i386/kvm/kvm.c
> +++ b/target/i386/kvm/kvm.c
> @@ -432,6 +432,11 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
> uint32_t eax;
> host_cpuid(7, 1, &eax, &unused, &unused, &unused);
> ret |= eax & (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC);
> + } else if (function == 7 && index == 2 && reg == R_EDX) {
> + /* Not new instructions, just an optimization. */
comment doesn't make much sense to me, just drop it or
describe what MCDT_NO is/mitigates.
> + uint32_t edx;
> + host_cpuid(7, 2, &unused, &unused, &unused, &edx);
> + ret |= edx & CPUID_7_2_EDX_MCDT_NO;
> } else if (function == 0xd && index == 0 &&
> (reg == R_EAX || reg == R_EDX)) {
> /*
next prev parent reply other threads:[~2023-06-26 13:04 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-16 3:23 [PATCH 0/7] Add new CPU model EmeraldRapids and GraniteRapids Tao Su
2023-06-16 3:23 ` [PATCH 1/7] target/i386: Add FEAT_7_1_EDX to adjust feature level Tao Su
2023-06-26 12:39 ` Igor Mammedov
2023-06-27 4:27 ` Tao Su
2023-06-27 8:28 ` Igor Mammedov
2023-06-16 3:23 ` [PATCH 2/7] target/i386: Add support for MCDT_NO in CPUID enumeration Tao Su
2023-06-16 3:23 ` [PATCH 3/7] target/i386: Allow MCDT_NO if host supports Tao Su
2023-06-26 13:03 ` Igor Mammedov [this message]
2023-06-27 4:31 ` Tao Su
2023-06-16 3:23 ` [PATCH 4/7] target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES Tao Su
2023-06-26 13:12 ` Igor Mammedov
2023-06-16 3:23 ` [PATCH 5/7] target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model Tao Su
2023-06-26 13:15 ` Igor Mammedov
2023-06-27 6:10 ` Xiaoyao Li
2023-06-27 8:29 ` Igor Mammedov
2023-06-16 3:23 ` [PATCH 6/7] target/i386: Add new CPU model EmeraldRapids Tao Su
2023-06-26 12:56 ` Igor Mammedov
2023-06-27 5:54 ` Xiaoyao Li
2023-06-27 8:49 ` Igor Mammedov
2023-06-27 11:25 ` Xiaoyao Li
2023-06-27 11:34 ` Daniel P. Berrangé
2023-06-16 3:23 ` [PATCH 7/7] target/i386: Add new CPU model GraniteRapids Tao Su
2023-06-27 11:55 ` Igor Mammedov
2023-06-28 6:11 ` Tao Su
2023-06-16 4:01 ` [PATCH 0/7] Add new CPU model EmeraldRapids and GraniteRapids Wang, Lei
2023-06-16 4:22 ` Tao Su
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