From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Anton Johansson <anjo@rev.ng>
Subject: [PULL 06/22] accel/tcg/cpu-exec.c: Widen pc to vaddr
Date: Mon, 26 Jun 2023 17:39:29 +0200 [thread overview]
Message-ID: <20230626153945.76180-7-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230626153945.76180-1-richard.henderson@linaro.org>
From: Anton Johansson <anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230621135633.1649-7-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/cpu-exec.c | 34 +++++++++++++++++-----------------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 4d952a6cc2..ba1890a373 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -169,8 +169,8 @@ uint32_t curr_cflags(CPUState *cpu)
}
struct tb_desc {
- target_ulong pc;
- target_ulong cs_base;
+ vaddr pc;
+ uint64_t cs_base;
CPUArchState *env;
tb_page_addr_t page_addr0;
uint32_t flags;
@@ -193,7 +193,7 @@ static bool tb_lookup_cmp(const void *p, const void *d)
return true;
} else {
tb_page_addr_t phys_page1;
- target_ulong virt_page1;
+ vaddr virt_page1;
/*
* We know that the first page matched, and an otherwise valid TB
@@ -214,8 +214,8 @@ static bool tb_lookup_cmp(const void *p, const void *d)
return false;
}
-static TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
- target_ulong cs_base, uint32_t flags,
+static TranslationBlock *tb_htable_lookup(CPUState *cpu, vaddr pc,
+ uint64_t cs_base, uint32_t flags,
uint32_t cflags)
{
tb_page_addr_t phys_pc;
@@ -238,9 +238,9 @@ static TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
}
/* Might cause an exception, so have a longjmp destination ready */
-static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
- target_ulong cs_base,
- uint32_t flags, uint32_t cflags)
+static inline TranslationBlock *tb_lookup(CPUState *cpu, vaddr pc,
+ uint64_t cs_base, uint32_t flags,
+ uint32_t cflags)
{
TranslationBlock *tb;
CPUJumpCache *jc;
@@ -292,13 +292,13 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
return tb;
}
-static void log_cpu_exec(target_ulong pc, CPUState *cpu,
+static void log_cpu_exec(vaddr pc, CPUState *cpu,
const TranslationBlock *tb)
{
if (qemu_log_in_addr_range(pc)) {
qemu_log_mask(CPU_LOG_EXEC,
"Trace %d: %p [%08" PRIx64
- "/" TARGET_FMT_lx "/%08x/%08x] %s\n",
+ "/%" VADDR_PRIx "/%08x/%08x] %s\n",
cpu->cpu_index, tb->tc.ptr, tb->cs_base, pc,
tb->flags, tb->cflags, lookup_symbol(pc));
@@ -323,7 +323,7 @@ static void log_cpu_exec(target_ulong pc, CPUState *cpu,
}
}
-static bool check_for_breakpoints_slow(CPUState *cpu, target_ulong pc,
+static bool check_for_breakpoints_slow(CPUState *cpu, vaddr pc,
uint32_t *cflags)
{
CPUBreakpoint *bp;
@@ -389,7 +389,7 @@ static bool check_for_breakpoints_slow(CPUState *cpu, target_ulong pc,
return false;
}
-static inline bool check_for_breakpoints(CPUState *cpu, target_ulong pc,
+static inline bool check_for_breakpoints(CPUState *cpu, vaddr pc,
uint32_t *cflags)
{
return unlikely(!QTAILQ_EMPTY(&cpu->breakpoints)) &&
@@ -485,10 +485,10 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
cc->set_pc(cpu, last_tb->pc);
}
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
- target_ulong pc = log_pc(cpu, last_tb);
+ vaddr pc = log_pc(cpu, last_tb);
if (qemu_log_in_addr_range(pc)) {
- qemu_log("Stopped execution of TB chain before %p ["
- TARGET_FMT_lx "] %s\n",
+ qemu_log("Stopped execution of TB chain before %p [%"
+ VADDR_PRIx "] %s\n",
last_tb->tc.ptr, pc, lookup_symbol(pc));
}
}
@@ -882,8 +882,8 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
}
static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb,
- target_ulong pc,
- TranslationBlock **last_tb, int *tb_exit)
+ vaddr pc, TranslationBlock **last_tb,
+ int *tb_exit)
{
int32_t insns_left;
--
2.34.1
next prev parent reply other threads:[~2023-06-26 15:48 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-26 15:39 [PULL 00/22] tcg patch queue Richard Henderson
2023-06-26 15:39 ` [PULL 01/22] accel: Replace target_ulong in tlb_*() Richard Henderson
2023-06-26 15:39 ` [PULL 02/22] accel/tcg/translate-all.c: Widen pc and cs_base Richard Henderson
2023-07-11 16:39 ` Peter Maydell
2023-06-26 15:39 ` [PULL 03/22] target: Widen pc/cs_base in cpu_get_tb_cpu_state Richard Henderson
2023-06-26 15:39 ` [PULL 04/22] accel/tcg/cputlb.c: Widen CPUTLBEntry access functions Richard Henderson
2023-06-26 15:39 ` [PULL 05/22] accel/tcg/cputlb.c: Widen addr in MMULookupPageData Richard Henderson
2023-06-26 15:39 ` Richard Henderson [this message]
2023-07-11 16:40 ` [PULL 06/22] accel/tcg/cpu-exec.c: Widen pc to vaddr Peter Maydell
2023-06-26 15:39 ` [PULL 07/22] accel/tcg: Widen pc to vaddr in CPUJumpCache Richard Henderson
2023-06-26 15:39 ` [PULL 08/22] accel: Replace target_ulong with vaddr in probe_*() Richard Henderson
2023-06-26 15:39 ` [PULL 09/22] accel/tcg: Replace target_ulong with vaddr in *_mmu_lookup() Richard Henderson
2023-06-26 15:39 ` [PULL 10/22] accel/tcg: Replace target_ulong with vaddr in translator_*() Richard Henderson
2023-06-26 15:39 ` [PULL 11/22] cpu: Replace target_ulong with hwaddr in tb_invalidate_phys_addr() Richard Henderson
2023-06-26 15:39 ` [PULL 12/22] softfloat: use QEMU_FLATTEN to avoid mistaken isra inlining Richard Henderson
2023-06-26 15:39 ` [PULL 13/22] tests/plugin: Remove duplicate insn log from libinsn.so Richard Henderson
2023-06-26 15:39 ` [PULL 14/22] accel/tcg: remove CONFIG_PROFILER Richard Henderson
2023-06-26 15:39 ` [PULL 15/22] tcg: Fix temporary variable in tcg_gen_gvec_andcs Richard Henderson
2023-06-26 15:39 ` [PULL 16/22] target/microblaze: Define TCG_GUEST_DEFAULT_MO Richard Henderson
2023-06-26 15:39 ` [PULL 17/22] tcg: Do not elide memory barriers for !CF_PARALLEL in system mode Richard Henderson
2023-06-26 15:39 ` [PULL 18/22] tcg: Add host memory barriers to cpu_ldst.h interfaces Richard Henderson
2023-06-26 15:39 ` [PULL 19/22] accel/tcg: Remove check_tcg_memory_orders_compatible Richard Henderson
2023-06-26 15:39 ` [PULL 20/22] accel/tcg: Store some tlb flags in CPUTLBEntryFull Richard Henderson
2023-06-26 15:39 ` [PULL 21/22] accel/tcg: Move TLB_WATCHPOINT to TLB_SLOW_FLAGS_MASK Richard Henderson
2023-06-26 15:39 ` [PULL 22/22] accel/tcg: Renumber TLB_DISCARD_WRITE Richard Henderson
2023-06-26 18:11 ` [PULL 00/22] tcg patch queue Richard Henderson
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