From: Igor Mammedov <imammedo@redhat.com>
To: Xiaoyao Li <xiaoyao.li@intel.com>
Cc: Tao Su <tao1.su@linux.intel.com>,
qemu-devel@nongnu.org, pbonzini@redhat.com, lei4.wang@intel.com,
qian.wen@intel.com
Subject: Re: [PATCH 5/7] target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model
Date: Tue, 27 Jun 2023 10:29:32 +0200 [thread overview]
Message-ID: <20230627102932.2a822b84@imammedo.users.ipa.redhat.com> (raw)
In-Reply-To: <f4b9bb58-a7d6-a02f-a307-450f3e630b3a@intel.com>
On Tue, 27 Jun 2023 14:10:17 +0800
Xiaoyao Li <xiaoyao.li@intel.com> wrote:
> On 6/26/2023 9:15 PM, Igor Mammedov wrote:
> > On Fri, 16 Jun 2023 11:23:09 +0800
> > Tao Su <tao1.su@linux.intel.com> wrote:
> >
> >> From: Lei Wang <lei4.wang@intel.com>
> >>
> >> Latest stepping (8) of SapphireRapids has bit 13, 14 and 15 of
> >> MSR_IA32_ARCH_CAPABILITIES enabled, which are related to some security
> >> fixes.
> >>
> >> Add version 2 of SapphireRapids CPU model with those bits enabled also.
> >
> > don't we need to update stepping value to 8 as well?
>
> No need.
>
> The commit message is misleading. There 3 bits and some other bits in
> MSR_IA32_ARCH_CAPABILITIES are not tied to CPU stepping. Instead, they
> are enumerated with newer microcode.
It that case fix commit message please.
>
> >>
> >> Signed-off-by: Lei Wang <lei4.wang@intel.com>
> >> Signed-off-by: Tao Su <tao1.su@linux.intel.com>
> >> ---
> >> target/i386/cpu.c | 13 +++++++++++--
> >> 1 file changed, 11 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> >> index b5321240c6..f84fd20bb1 100644
> >> --- a/target/i386/cpu.c
> >> +++ b/target/i386/cpu.c
> >> @@ -3854,8 +3854,17 @@ static const X86CPUDefinition builtin_x86_defs[] = {
> >> .model_id = "Intel Xeon Processor (SapphireRapids)",
> >> .versions = (X86CPUVersionDefinition[]) {
> >> { .version = 1 },
> >> - { /* end of list */ },
> >> - },
> >> + {
> >> + .version = 2,
> >> + .props = (PropValue[]) {
> >> + { "sbdr-ssdp-no", "on" },
> >> + { "fbsdp-no", "on" },
> >> + { "psdp-no", "on" },
> >> + { /* end of list */ }
> >> + }
> >> + },
> >> + { /* end of list */ }
> >> + }
> >> },
> >> {
> >> .name = "Denverton",
> >
>
next prev parent reply other threads:[~2023-06-27 8:30 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-16 3:23 [PATCH 0/7] Add new CPU model EmeraldRapids and GraniteRapids Tao Su
2023-06-16 3:23 ` [PATCH 1/7] target/i386: Add FEAT_7_1_EDX to adjust feature level Tao Su
2023-06-26 12:39 ` Igor Mammedov
2023-06-27 4:27 ` Tao Su
2023-06-27 8:28 ` Igor Mammedov
2023-06-16 3:23 ` [PATCH 2/7] target/i386: Add support for MCDT_NO in CPUID enumeration Tao Su
2023-06-16 3:23 ` [PATCH 3/7] target/i386: Allow MCDT_NO if host supports Tao Su
2023-06-26 13:03 ` Igor Mammedov
2023-06-27 4:31 ` Tao Su
2023-06-16 3:23 ` [PATCH 4/7] target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES Tao Su
2023-06-26 13:12 ` Igor Mammedov
2023-06-16 3:23 ` [PATCH 5/7] target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model Tao Su
2023-06-26 13:15 ` Igor Mammedov
2023-06-27 6:10 ` Xiaoyao Li
2023-06-27 8:29 ` Igor Mammedov [this message]
2023-06-16 3:23 ` [PATCH 6/7] target/i386: Add new CPU model EmeraldRapids Tao Su
2023-06-26 12:56 ` Igor Mammedov
2023-06-27 5:54 ` Xiaoyao Li
2023-06-27 8:49 ` Igor Mammedov
2023-06-27 11:25 ` Xiaoyao Li
2023-06-27 11:34 ` Daniel P. Berrangé
2023-06-16 3:23 ` [PATCH 7/7] target/i386: Add new CPU model GraniteRapids Tao Su
2023-06-27 11:55 ` Igor Mammedov
2023-06-28 6:11 ` Tao Su
2023-06-16 4:01 ` [PATCH 0/7] Add new CPU model EmeraldRapids and GraniteRapids Wang, Lei
2023-06-16 4:22 ` Tao Su
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