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[213.175.37.10]) by smtp.gmail.com with ESMTPSA id f11-20020a170906084b00b00991e019207esm1665678ejd.55.2023.06.27.01.29.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jun 2023 01:29:32 -0700 (PDT) Date: Tue, 27 Jun 2023 10:29:32 +0200 From: Igor Mammedov To: Xiaoyao Li Cc: Tao Su , qemu-devel@nongnu.org, pbonzini@redhat.com, lei4.wang@intel.com, qian.wen@intel.com Subject: Re: [PATCH 5/7] target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model Message-ID: <20230627102932.2a822b84@imammedo.users.ipa.redhat.com> In-Reply-To: References: <20230616032311.19137-1-tao1.su@linux.intel.com> <20230616032311.19137-6-tao1.su@linux.intel.com> <20230626151530.24524700@imammedo.users.ipa.redhat.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, 27 Jun 2023 14:10:17 +0800 Xiaoyao Li wrote: > On 6/26/2023 9:15 PM, Igor Mammedov wrote: > > On Fri, 16 Jun 2023 11:23:09 +0800 > > Tao Su wrote: > > > >> From: Lei Wang > >> > >> Latest stepping (8) of SapphireRapids has bit 13, 14 and 15 of > >> MSR_IA32_ARCH_CAPABILITIES enabled, which are related to some security > >> fixes. > >> > >> Add version 2 of SapphireRapids CPU model with those bits enabled also. > > > > don't we need to update stepping value to 8 as well? > > No need. > > The commit message is misleading. There 3 bits and some other bits in > MSR_IA32_ARCH_CAPABILITIES are not tied to CPU stepping. Instead, they > are enumerated with newer microcode. It that case fix commit message please. > > >> > >> Signed-off-by: Lei Wang > >> Signed-off-by: Tao Su > >> --- > >> target/i386/cpu.c | 13 +++++++++++-- > >> 1 file changed, 11 insertions(+), 2 deletions(-) > >> > >> diff --git a/target/i386/cpu.c b/target/i386/cpu.c > >> index b5321240c6..f84fd20bb1 100644 > >> --- a/target/i386/cpu.c > >> +++ b/target/i386/cpu.c > >> @@ -3854,8 +3854,17 @@ static const X86CPUDefinition builtin_x86_defs[] = { > >> .model_id = "Intel Xeon Processor (SapphireRapids)", > >> .versions = (X86CPUVersionDefinition[]) { > >> { .version = 1 }, > >> - { /* end of list */ }, > >> - }, > >> + { > >> + .version = 2, > >> + .props = (PropValue[]) { > >> + { "sbdr-ssdp-no", "on" }, > >> + { "fbsdp-no", "on" }, > >> + { "psdp-no", "on" }, > >> + { /* end of list */ } > >> + } > >> + }, > >> + { /* end of list */ } > >> + } > >> }, > >> { > >> .name = "Denverton", > > >