From: Max Chou <max.chou@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: dbarboza@ventanamicro.com,
Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>,
Weiwei Li <liweiwei@iscas.ac.cn>, Max Chou <max.chou@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Bin Meng <bin.meng@windriver.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Junqiang Wang <wangjunqiang@iscas.ac.cn>
Subject: [PATCH v6 02/15] target/riscv: Refactor vector-vector translation macro
Date: Wed, 28 Jun 2023 01:45:36 +0800 [thread overview]
Message-ID: <20230627174551.65498-3-max.chou@sifive.com> (raw)
In-Reply-To: <20230627174551.65498-1-max.chou@sifive.com>
From: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Refactor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into
function `opivv_trans` (similar to `opivi_trans`). `opivv_trans` will be
used in proceeding vector-crypto commits.
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 62 +++++++++++++------------
1 file changed, 32 insertions(+), 30 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index c2f7527f53..4a8e62a8be 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1643,38 +1643,40 @@ GEN_OPIWX_WIDEN_TRANS(vwadd_wx)
GEN_OPIWX_WIDEN_TRANS(vwsubu_wx)
GEN_OPIWX_WIDEN_TRANS(vwsub_wx)
+static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
+ gen_helper_gvec_4_ptr *fn, DisasContext *s)
+{
+ uint32_t data = 0;
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
+
+ data = FIELD_DP32(data, VDATA, VM, vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
+ tcg_gen_gvec_4_ptr(vreg_ofs(s, vd), vreg_ofs(s, 0), vreg_ofs(s, vs1),
+ vreg_ofs(s, vs2), cpu_env, s->cfg_ptr->vlen / 8,
+ s->cfg_ptr->vlen / 8, data, fn);
+ mark_vs_dirty(s);
+ gen_set_label(over);
+ return true;
+}
+
/* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */
/* OPIVV without GVEC IR */
-#define GEN_OPIVV_TRANS(NAME, CHECK) \
-static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
-{ \
- if (CHECK(s, a)) { \
- uint32_t data = 0; \
- static gen_helper_gvec_4_ptr * const fns[4] = { \
- gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
- gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
- }; \
- TCGLabel *over = gen_new_label(); \
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
- \
- data = FIELD_DP32(data, VDATA, VM, a->vm); \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- data = FIELD_DP32(data, VDATA, VTA, s->vta); \
- data = \
- FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
- data = FIELD_DP32(data, VDATA, VMA, s->vma); \
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs1), \
- vreg_ofs(s, a->rs2), cpu_env, \
- s->cfg_ptr->vlen / 8, \
- s->cfg_ptr->vlen / 8, data, \
- fns[s->sew]); \
- mark_vs_dirty(s); \
- gen_set_label(over); \
- return true; \
- } \
- return false; \
+#define GEN_OPIVV_TRANS(NAME, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ if (CHECK(s, a)) { \
+ static gen_helper_gvec_4_ptr * const fns[4] = { \
+ gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
+ }; \
+ return opivv_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\
+ } \
+ return false; \
}
/*
--
2.31.1
next prev parent reply other threads:[~2023-06-27 17:48 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-27 17:45 [PATCH v5 00/15] Add RISC-V vector cryptographic instruction set support Max Chou
2023-06-27 17:45 ` [PATCH v6 01/15] target/riscv: Refactor some of the generic vector functionality Max Chou
2023-06-27 17:45 ` Max Chou [this message]
2023-06-27 17:45 ` [PATCH v6 03/15] target/riscv: Remove redundant "cpu_vl == 0" checks Max Chou
2023-06-27 17:45 ` [PATCH v6 04/15] target/riscv: Add Zvbc ISA extension support Max Chou
2023-06-27 17:45 ` [PATCH v6 05/15] target/riscv: Move vector translation checks Max Chou
2023-06-27 17:45 ` [PATCH v6 06/15] target/riscv: Refactor translation of vector-widening instruction Max Chou
2023-06-27 17:45 ` [PATCH v6 07/15] target/riscv: Refactor some of the generic vector functionality Max Chou
2023-06-27 17:45 ` [PATCH v6 08/15] target/riscv: Add Zvbb ISA extension support Max Chou
2023-06-27 17:45 ` [PATCH v6 09/15] target/riscv: Add Zvkned " Max Chou
2023-06-28 9:07 ` Richard Henderson
2023-06-29 15:10 ` Max Chou
2023-06-29 16:25 ` Richard Henderson
2023-06-27 17:45 ` [PATCH v6 10/15] target/riscv: Add Zvknh " Max Chou
2023-06-28 9:14 ` Richard Henderson
2023-06-29 11:06 ` Max Chou
2023-06-27 17:45 ` [PATCH v6 11/15] target/riscv: Add Zvksh " Max Chou
2023-06-27 17:45 ` [PATCH v6 12/15] target/riscv: Add Zvkg " Max Chou
2023-06-27 17:45 ` [PATCH v6 13/15] crypto: Create sm4_subword Max Chou
2023-06-27 17:45 ` [PATCH v6 14/15] crypto: Add SM4 constant parameter CK Max Chou
2023-06-27 17:45 ` [PATCH v6 15/15] target/riscv: Add Zvksed ISA extension support Max Chou
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230627174551.65498-3-max.chou@sifive.com \
--to=max.chou@sifive.com \
--cc=alistair.francis@wdc.com \
--cc=bin.meng@windriver.com \
--cc=dbarboza@ventanamicro.com \
--cc=kiran.ostrolenk@codethink.co.uk \
--cc=liweiwei@iscas.ac.cn \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=wangjunqiang@iscas.ac.cn \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).