From: Max Chou <max.chou@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: dbarboza@ventanamicro.com,
Dickon Hood <dickon.hood@codethink.co.uk>,
Richard Henderson <richard.henderson@linaro.org>,
Weiwei Li <liweiwei@iscas.ac.cn>, Max Chou <max.chou@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Junqiang Wang <wangjunqiang@iscas.ac.cn>
Subject: [PATCH v6 06/15] target/riscv: Refactor translation of vector-widening instruction
Date: Wed, 28 Jun 2023 01:45:40 +0800 [thread overview]
Message-ID: <20230627174551.65498-7-max.chou@sifive.com> (raw)
In-Reply-To: <20230627174551.65498-1-max.chou@sifive.com>
From: Dickon Hood <dickon.hood@codethink.co.uk>
Zvbb (implemented in later commit) has a widening instruction, which
requires an extra check on the enabled extensions. Refactor
GEN_OPIVX_WIDEN_TRANS() to take a check function to avoid reimplementing
it.
Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 52 +++++++++++--------------
1 file changed, 23 insertions(+), 29 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 5dfd524c7d..a556250553 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1526,30 +1526,24 @@ static bool opivx_widen_check(DisasContext *s, arg_rmrr *a)
vext_check_ds(s, a->rd, a->rs2, a->vm);
}
-static bool do_opivx_widen(DisasContext *s, arg_rmrr *a,
- gen_helper_opivx *fn)
-{
- if (opivx_widen_check(s, a)) {
- return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
- }
- return false;
-}
-
-#define GEN_OPIVX_WIDEN_TRANS(NAME) \
-static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
-{ \
- static gen_helper_opivx * const fns[3] = { \
- gen_helper_##NAME##_b, \
- gen_helper_##NAME##_h, \
- gen_helper_##NAME##_w \
- }; \
- return do_opivx_widen(s, a, fns[s->sew]); \
+#define GEN_OPIVX_WIDEN_TRANS(NAME, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ if (CHECK(s, a)) { \
+ static gen_helper_opivx * const fns[3] = { \
+ gen_helper_##NAME##_b, \
+ gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w \
+ }; \
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s); \
+ } \
+ return false; \
}
-GEN_OPIVX_WIDEN_TRANS(vwaddu_vx)
-GEN_OPIVX_WIDEN_TRANS(vwadd_vx)
-GEN_OPIVX_WIDEN_TRANS(vwsubu_vx)
-GEN_OPIVX_WIDEN_TRANS(vwsub_vx)
+GEN_OPIVX_WIDEN_TRANS(vwaddu_vx, opivx_widen_check)
+GEN_OPIVX_WIDEN_TRANS(vwadd_vx, opivx_widen_check)
+GEN_OPIVX_WIDEN_TRANS(vwsubu_vx, opivx_widen_check)
+GEN_OPIVX_WIDEN_TRANS(vwsub_vx, opivx_widen_check)
/* WIDEN OPIVV with WIDEN */
static bool opiwv_widen_check(DisasContext *s, arg_rmrr *a)
@@ -1997,9 +1991,9 @@ GEN_OPIVX_TRANS(vrem_vx, opivx_check)
GEN_OPIVV_WIDEN_TRANS(vwmul_vv, opivv_widen_check)
GEN_OPIVV_WIDEN_TRANS(vwmulu_vv, opivv_widen_check)
GEN_OPIVV_WIDEN_TRANS(vwmulsu_vv, opivv_widen_check)
-GEN_OPIVX_WIDEN_TRANS(vwmul_vx)
-GEN_OPIVX_WIDEN_TRANS(vwmulu_vx)
-GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx)
+GEN_OPIVX_WIDEN_TRANS(vwmul_vx, opivx_widen_check)
+GEN_OPIVX_WIDEN_TRANS(vwmulu_vx, opivx_widen_check)
+GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx, opivx_widen_check)
/* Vector Single-Width Integer Multiply-Add Instructions */
GEN_OPIVV_TRANS(vmacc_vv, opivv_check)
@@ -2015,10 +2009,10 @@ GEN_OPIVX_TRANS(vnmsub_vx, opivx_check)
GEN_OPIVV_WIDEN_TRANS(vwmaccu_vv, opivv_widen_check)
GEN_OPIVV_WIDEN_TRANS(vwmacc_vv, opivv_widen_check)
GEN_OPIVV_WIDEN_TRANS(vwmaccsu_vv, opivv_widen_check)
-GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx)
-GEN_OPIVX_WIDEN_TRANS(vwmacc_vx)
-GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx)
-GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx)
+GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx, opivx_widen_check)
+GEN_OPIVX_WIDEN_TRANS(vwmacc_vx, opivx_widen_check)
+GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx, opivx_widen_check)
+GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx, opivx_widen_check)
/* Vector Integer Merge and Move Instructions */
static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
--
2.31.1
next prev parent reply other threads:[~2023-06-27 17:48 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-27 17:45 [PATCH v5 00/15] Add RISC-V vector cryptographic instruction set support Max Chou
2023-06-27 17:45 ` [PATCH v6 01/15] target/riscv: Refactor some of the generic vector functionality Max Chou
2023-06-27 17:45 ` [PATCH v6 02/15] target/riscv: Refactor vector-vector translation macro Max Chou
2023-06-27 17:45 ` [PATCH v6 03/15] target/riscv: Remove redundant "cpu_vl == 0" checks Max Chou
2023-06-27 17:45 ` [PATCH v6 04/15] target/riscv: Add Zvbc ISA extension support Max Chou
2023-06-27 17:45 ` [PATCH v6 05/15] target/riscv: Move vector translation checks Max Chou
2023-06-27 17:45 ` Max Chou [this message]
2023-06-27 17:45 ` [PATCH v6 07/15] target/riscv: Refactor some of the generic vector functionality Max Chou
2023-06-27 17:45 ` [PATCH v6 08/15] target/riscv: Add Zvbb ISA extension support Max Chou
2023-06-27 17:45 ` [PATCH v6 09/15] target/riscv: Add Zvkned " Max Chou
2023-06-28 9:07 ` Richard Henderson
2023-06-29 15:10 ` Max Chou
2023-06-29 16:25 ` Richard Henderson
2023-06-27 17:45 ` [PATCH v6 10/15] target/riscv: Add Zvknh " Max Chou
2023-06-28 9:14 ` Richard Henderson
2023-06-29 11:06 ` Max Chou
2023-06-27 17:45 ` [PATCH v6 11/15] target/riscv: Add Zvksh " Max Chou
2023-06-27 17:45 ` [PATCH v6 12/15] target/riscv: Add Zvkg " Max Chou
2023-06-27 17:45 ` [PATCH v6 13/15] crypto: Create sm4_subword Max Chou
2023-06-27 17:45 ` [PATCH v6 14/15] crypto: Add SM4 constant parameter CK Max Chou
2023-06-27 17:45 ` [PATCH v6 15/15] target/riscv: Add Zvksed ISA extension support Max Chou
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