* [PATCH v5 1/1] target/riscv: Add RVV registers to log
@ 2023-06-29 8:37 Ivan Klokov
2023-06-29 12:34 ` Daniel Henrique Barboza
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Ivan Klokov @ 2023-06-29 8:37 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, richard.henderson, pbonzini, eduardo,
marcel.apfelbaum, philmd, wangyanan55, palmer, alistair.francis,
bin.meng, liweiwei, dbarboza, zhiwei_liu, Ivan Klokov
Print RvV extension register to log if VPU option is enabled.
Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
---
v5:
- Fix typo, move macros out of function, direct access to cfg.vlen field.
---
target/riscv/cpu.c | 57 +++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 56 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 881bddf393..ff29573b1f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -55,6 +55,17 @@ struct isa_ext_data {
#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
{#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
+/*
+ * From vector_helper.c
+ * Note that vector data is stored in host-endian 64-bit chunks,
+ * so addressing bytes needs a host-endian fixup.
+ */
+#if HOST_BIG_ENDIAN
+#define BYTE(x) ((x) ^ 7)
+#else
+#define BYTE(x) (x)
+#endif
+
/*
* Here are the ordering rules of extension naming defined by RISC-V
* specification :
@@ -183,6 +194,14 @@ const char * const riscv_fpr_regnames[] = {
"f30/ft10", "f31/ft11"
};
+const char * const riscv_rvv_regnames[] = {
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6",
+ "v7", "v8", "v9", "v10", "v11", "v12", "v13",
+ "v14", "v15", "v16", "v17", "v18", "v19", "v20",
+ "v21", "v22", "v23", "v24", "v25", "v26", "v27",
+ "v28", "v29", "v30", "v31"
+};
+
static const char * const riscv_excp_names[] = {
"misaligned_fetch",
"fault_fetch",
@@ -608,7 +627,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
- int i;
+ int i, j;
+ uint8_t *p;
#if !defined(CONFIG_USER_ONLY)
if (riscv_has_ext(env, RVH)) {
@@ -692,6 +712,41 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
}
}
+ if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) {
+ static const int dump_rvv_csrs[] = {
+ CSR_VSTART,
+ CSR_VXSAT,
+ CSR_VXRM,
+ CSR_VCSR,
+ CSR_VL,
+ CSR_VTYPE,
+ CSR_VLENB,
+ };
+ for (int i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) {
+ int csrno = dump_rvv_csrs[i];
+ target_ulong val = 0;
+ RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
+
+ /*
+ * Rely on the smode, hmode, etc, predicates within csr.c
+ * to do the filtering of the registers that are present.
+ */
+ if (res == RISCV_EXCP_NONE) {
+ qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
+ csr_ops[csrno].name, val);
+ }
+ }
+ uint16_t vlenb = cpu->cfg.vlen >> 3;
+
+ for (i = 0; i < 32; i++) {
+ qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]);
+ p = (uint8_t *)env->vreg;
+ for (j = vlenb - 1 ; j >= 0; j--) {
+ qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j)));
+ }
+ qemu_fprintf(f, "\n");
+ }
+ }
}
static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v5 1/1] target/riscv: Add RVV registers to log
2023-06-29 8:37 [PATCH v5 1/1] target/riscv: Add RVV registers to log Ivan Klokov
@ 2023-06-29 12:34 ` Daniel Henrique Barboza
2023-07-03 2:28 ` Alistair Francis
2023-07-03 2:37 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Daniel Henrique Barboza @ 2023-06-29 12:34 UTC (permalink / raw)
To: Ivan Klokov, qemu-devel
Cc: qemu-riscv, richard.henderson, pbonzini, eduardo,
marcel.apfelbaum, philmd, wangyanan55, palmer, alistair.francis,
bin.meng, liweiwei, zhiwei_liu
On 6/29/23 05:37, Ivan Klokov wrote:
> Print RvV extension register to log if VPU option is enabled.
>
> Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
> ---
> v5:
> - Fix typo, move macros out of function, direct access to cfg.vlen field.
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/cpu.c | 57 +++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 56 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 881bddf393..ff29573b1f 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -55,6 +55,17 @@ struct isa_ext_data {
> #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
> {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
>
> +/*
> + * From vector_helper.c
> + * Note that vector data is stored in host-endian 64-bit chunks,
> + * so addressing bytes needs a host-endian fixup.
> + */
> +#if HOST_BIG_ENDIAN
> +#define BYTE(x) ((x) ^ 7)
> +#else
> +#define BYTE(x) (x)
> +#endif
> +
> /*
> * Here are the ordering rules of extension naming defined by RISC-V
> * specification :
> @@ -183,6 +194,14 @@ const char * const riscv_fpr_regnames[] = {
> "f30/ft10", "f31/ft11"
> };
>
> +const char * const riscv_rvv_regnames[] = {
> + "v0", "v1", "v2", "v3", "v4", "v5", "v6",
> + "v7", "v8", "v9", "v10", "v11", "v12", "v13",
> + "v14", "v15", "v16", "v17", "v18", "v19", "v20",
> + "v21", "v22", "v23", "v24", "v25", "v26", "v27",
> + "v28", "v29", "v30", "v31"
> +};
> +
> static const char * const riscv_excp_names[] = {
> "misaligned_fetch",
> "fault_fetch",
> @@ -608,7 +627,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
> {
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> - int i;
> + int i, j;
> + uint8_t *p;
>
> #if !defined(CONFIG_USER_ONLY)
> if (riscv_has_ext(env, RVH)) {
> @@ -692,6 +712,41 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
> }
> }
> }
> + if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) {
> + static const int dump_rvv_csrs[] = {
> + CSR_VSTART,
> + CSR_VXSAT,
> + CSR_VXRM,
> + CSR_VCSR,
> + CSR_VL,
> + CSR_VTYPE,
> + CSR_VLENB,
> + };
> + for (int i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) {
> + int csrno = dump_rvv_csrs[i];
> + target_ulong val = 0;
> + RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
> +
> + /*
> + * Rely on the smode, hmode, etc, predicates within csr.c
> + * to do the filtering of the registers that are present.
> + */
> + if (res == RISCV_EXCP_NONE) {
> + qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
> + csr_ops[csrno].name, val);
> + }
> + }
> + uint16_t vlenb = cpu->cfg.vlen >> 3;
> +
> + for (i = 0; i < 32; i++) {
> + qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]);
> + p = (uint8_t *)env->vreg;
> + for (j = vlenb - 1 ; j >= 0; j--) {
> + qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j)));
> + }
> + qemu_fprintf(f, "\n");
> + }
> + }
> }
>
> static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v5 1/1] target/riscv: Add RVV registers to log
2023-06-29 8:37 [PATCH v5 1/1] target/riscv: Add RVV registers to log Ivan Klokov
2023-06-29 12:34 ` Daniel Henrique Barboza
@ 2023-07-03 2:28 ` Alistair Francis
2023-07-03 2:37 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2023-07-03 2:28 UTC (permalink / raw)
To: Ivan Klokov
Cc: qemu-devel, qemu-riscv, richard.henderson, pbonzini, eduardo,
marcel.apfelbaum, philmd, wangyanan55, palmer, alistair.francis,
bin.meng, liweiwei, dbarboza, zhiwei_liu
On Thu, Jun 29, 2023 at 6:39 PM Ivan Klokov <ivan.klokov@syntacore.com> wrote:
>
> Print RvV extension register to log if VPU option is enabled.
>
> Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> v5:
> - Fix typo, move macros out of function, direct access to cfg.vlen field.
> ---
> target/riscv/cpu.c | 57 +++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 56 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 881bddf393..ff29573b1f 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -55,6 +55,17 @@ struct isa_ext_data {
> #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
> {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
>
> +/*
> + * From vector_helper.c
> + * Note that vector data is stored in host-endian 64-bit chunks,
> + * so addressing bytes needs a host-endian fixup.
> + */
> +#if HOST_BIG_ENDIAN
> +#define BYTE(x) ((x) ^ 7)
> +#else
> +#define BYTE(x) (x)
> +#endif
> +
> /*
> * Here are the ordering rules of extension naming defined by RISC-V
> * specification :
> @@ -183,6 +194,14 @@ const char * const riscv_fpr_regnames[] = {
> "f30/ft10", "f31/ft11"
> };
>
> +const char * const riscv_rvv_regnames[] = {
> + "v0", "v1", "v2", "v3", "v4", "v5", "v6",
> + "v7", "v8", "v9", "v10", "v11", "v12", "v13",
> + "v14", "v15", "v16", "v17", "v18", "v19", "v20",
> + "v21", "v22", "v23", "v24", "v25", "v26", "v27",
> + "v28", "v29", "v30", "v31"
> +};
> +
> static const char * const riscv_excp_names[] = {
> "misaligned_fetch",
> "fault_fetch",
> @@ -608,7 +627,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
> {
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> - int i;
> + int i, j;
> + uint8_t *p;
>
> #if !defined(CONFIG_USER_ONLY)
> if (riscv_has_ext(env, RVH)) {
> @@ -692,6 +712,41 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
> }
> }
> }
> + if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) {
> + static const int dump_rvv_csrs[] = {
> + CSR_VSTART,
> + CSR_VXSAT,
> + CSR_VXRM,
> + CSR_VCSR,
> + CSR_VL,
> + CSR_VTYPE,
> + CSR_VLENB,
> + };
> + for (int i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) {
> + int csrno = dump_rvv_csrs[i];
> + target_ulong val = 0;
> + RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
> +
> + /*
> + * Rely on the smode, hmode, etc, predicates within csr.c
> + * to do the filtering of the registers that are present.
> + */
> + if (res == RISCV_EXCP_NONE) {
> + qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
> + csr_ops[csrno].name, val);
> + }
> + }
> + uint16_t vlenb = cpu->cfg.vlen >> 3;
> +
> + for (i = 0; i < 32; i++) {
> + qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]);
> + p = (uint8_t *)env->vreg;
> + for (j = vlenb - 1 ; j >= 0; j--) {
> + qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j)));
> + }
> + qemu_fprintf(f, "\n");
> + }
> + }
> }
>
> static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v5 1/1] target/riscv: Add RVV registers to log
2023-06-29 8:37 [PATCH v5 1/1] target/riscv: Add RVV registers to log Ivan Klokov
2023-06-29 12:34 ` Daniel Henrique Barboza
2023-07-03 2:28 ` Alistair Francis
@ 2023-07-03 2:37 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2023-07-03 2:37 UTC (permalink / raw)
To: Ivan Klokov
Cc: qemu-devel, qemu-riscv, richard.henderson, pbonzini, eduardo,
marcel.apfelbaum, philmd, wangyanan55, palmer, alistair.francis,
bin.meng, liweiwei, dbarboza, zhiwei_liu
On Thu, Jun 29, 2023 at 6:39 PM Ivan Klokov <ivan.klokov@syntacore.com> wrote:
>
> Print RvV extension register to log if VPU option is enabled.
>
> Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> v5:
> - Fix typo, move macros out of function, direct access to cfg.vlen field.
> ---
> target/riscv/cpu.c | 57 +++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 56 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 881bddf393..ff29573b1f 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -55,6 +55,17 @@ struct isa_ext_data {
> #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
> {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
>
> +/*
> + * From vector_helper.c
> + * Note that vector data is stored in host-endian 64-bit chunks,
> + * so addressing bytes needs a host-endian fixup.
> + */
> +#if HOST_BIG_ENDIAN
> +#define BYTE(x) ((x) ^ 7)
> +#else
> +#define BYTE(x) (x)
> +#endif
> +
> /*
> * Here are the ordering rules of extension naming defined by RISC-V
> * specification :
> @@ -183,6 +194,14 @@ const char * const riscv_fpr_regnames[] = {
> "f30/ft10", "f31/ft11"
> };
>
> +const char * const riscv_rvv_regnames[] = {
> + "v0", "v1", "v2", "v3", "v4", "v5", "v6",
> + "v7", "v8", "v9", "v10", "v11", "v12", "v13",
> + "v14", "v15", "v16", "v17", "v18", "v19", "v20",
> + "v21", "v22", "v23", "v24", "v25", "v26", "v27",
> + "v28", "v29", "v30", "v31"
> +};
> +
> static const char * const riscv_excp_names[] = {
> "misaligned_fetch",
> "fault_fetch",
> @@ -608,7 +627,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
> {
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> - int i;
> + int i, j;
> + uint8_t *p;
>
> #if !defined(CONFIG_USER_ONLY)
> if (riscv_has_ext(env, RVH)) {
> @@ -692,6 +712,41 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
> }
> }
> }
> + if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) {
> + static const int dump_rvv_csrs[] = {
> + CSR_VSTART,
> + CSR_VXSAT,
> + CSR_VXRM,
> + CSR_VCSR,
> + CSR_VL,
> + CSR_VTYPE,
> + CSR_VLENB,
> + };
> + for (int i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) {
> + int csrno = dump_rvv_csrs[i];
> + target_ulong val = 0;
> + RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
> +
> + /*
> + * Rely on the smode, hmode, etc, predicates within csr.c
> + * to do the filtering of the registers that are present.
> + */
> + if (res == RISCV_EXCP_NONE) {
> + qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
> + csr_ops[csrno].name, val);
> + }
> + }
> + uint16_t vlenb = cpu->cfg.vlen >> 3;
> +
> + for (i = 0; i < 32; i++) {
> + qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]);
> + p = (uint8_t *)env->vreg;
> + for (j = vlenb - 1 ; j >= 0; j--) {
> + qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j)));
> + }
> + qemu_fprintf(f, "\n");
> + }
> + }
> }
>
> static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
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2023-06-29 8:37 [PATCH v5 1/1] target/riscv: Add RVV registers to log Ivan Klokov
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