From: Frederic Barrat <fbarrat@linux.ibm.com>
To: "Cédric Le Goater" <clg@kaod.org>,
"Daniel Henrique Barboza" <danielhb413@gmail.com>,
qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH 2/2] pnv/psi: Initialize the PSIHB interrupts to match hardware
Date: Fri, 30 Jun 2023 16:42:42 +0200 [thread overview]
Message-ID: <20230630144243.214976-3-fbarrat@linux.ibm.com> (raw)
In-Reply-To: <20230630144243.214976-1-fbarrat@linux.ibm.com>
On P9/P10, the PSIHB interrupts are initialized with a PQ state of
0b01, i.e. interrupts are disabled. However the real hardware
initializes them to 0b00 for the PSIHB. This patch updates it, in case
an hypervisor is in the mood of checking it.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
---
hw/ppc/pnv_psi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index 46da58dff8..f232935d27 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -863,6 +863,8 @@ static void pnv_psi_power9_realize(DeviceState *dev, Error **errp)
object_property_set_int(OBJECT(xsrc), "nr-irqs", PSIHB9_NUM_IRQS,
&error_fatal);
object_property_set_link(OBJECT(xsrc), "xive", OBJECT(psi), &error_abort);
+ object_property_set_int(OBJECT(xsrc), "pq-init", XIVE_ESB_RESET,
+ &error_abort);
if (!qdev_realize(DEVICE(xsrc), NULL, errp)) {
return;
}
--
2.41.0
next prev parent reply other threads:[~2023-06-30 14:43 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-30 14:42 [PATCH 0/2] Fix PSIHB interrupts init PQ state Frederic Barrat
2023-06-30 14:42 ` [PATCH 1/2] pnv/xive: Add property on xive sources to define PQ state on reset Frederic Barrat
2023-06-30 14:58 ` Cédric Le Goater
2023-06-30 14:42 ` Frederic Barrat [this message]
2023-06-30 14:59 ` [PATCH 2/2] pnv/psi: Initialize the PSIHB interrupts to match hardware Cédric Le Goater
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