* [PATCH v2 1/5] ppc/pnv: quad xscom callbacks are P9 specific
2023-07-04 5:41 [PATCH v2 0/5] ppc/pnv: Extend "quad" model for p10 Joel Stanley
@ 2023-07-04 5:42 ` Joel Stanley
2023-07-04 9:59 ` Frederic Barrat
2023-07-04 5:42 ` [PATCH v2 2/5] ppc/pnv: Subclass quad xscom callbacks Joel Stanley
` (5 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Joel Stanley @ 2023-07-04 5:42 UTC (permalink / raw)
To: Cédric Le Goater, Nicholas Piggin, Frédéric Barrat
Cc: qemu-devel, qemu-ppc
Rename the functions to include P9 in the name in preparation for adding
P10 versions.
Correct the unimp read message while we're changing the function.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
v2: Fix unimp print, and grammar in the commit message
---
hw/ppc/pnv_core.c | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 0bc3ad41c81c..0f451b3b6e1f 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -360,8 +360,8 @@ DEFINE_TYPES(pnv_core_infos)
#define P9X_EX_NCU_SPEC_BAR 0x11010
-static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr,
- unsigned int width)
+static uint64_t pnv_quad_power9_xscom_read(void *opaque, hwaddr addr,
+ unsigned int width)
{
uint32_t offset = addr >> 3;
uint64_t val = -1;
@@ -372,15 +372,15 @@ static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr,
val = 0;
break;
default:
- qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
+ qemu_log_mask(LOG_UNIMP, "%s: reading @0x%08x\n", __func__,
offset);
}
return val;
}
-static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val,
- unsigned int width)
+static void pnv_quad_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned int width)
{
uint32_t offset = addr >> 3;
@@ -394,9 +394,9 @@ static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val,
}
}
-static const MemoryRegionOps pnv_quad_xscom_ops = {
- .read = pnv_quad_xscom_read,
- .write = pnv_quad_xscom_write,
+static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
+ .read = pnv_quad_power9_xscom_read,
+ .write = pnv_quad_power9_xscom_write,
.valid.min_access_size = 8,
.valid.max_access_size = 8,
.impl.min_access_size = 8,
@@ -410,7 +410,8 @@ static void pnv_quad_realize(DeviceState *dev, Error **errp)
char name[32];
snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id);
- pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops,
+ pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev),
+ &pnv_quad_power9_xscom_ops,
eq, name, PNV9_XSCOM_EQ_SIZE);
}
--
2.40.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v2 1/5] ppc/pnv: quad xscom callbacks are P9 specific
2023-07-04 5:42 ` [PATCH v2 1/5] ppc/pnv: quad xscom callbacks are P9 specific Joel Stanley
@ 2023-07-04 9:59 ` Frederic Barrat
0 siblings, 0 replies; 15+ messages in thread
From: Frederic Barrat @ 2023-07-04 9:59 UTC (permalink / raw)
To: Joel Stanley, Cédric Le Goater, Nicholas Piggin; +Cc: qemu-devel, qemu-ppc
On 04/07/2023 07:42, Joel Stanley wrote:
> Rename the functions to include P9 in the name in preparation for adding
> P10 versions.
>
> Correct the unimp read message while we're changing the function.
>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
> v2: Fix unimp print, and grammar in the commit message
> ---
> hw/ppc/pnv_core.c | 19 ++++++++++---------
> 1 file changed, 10 insertions(+), 9 deletions(-)
>
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index 0bc3ad41c81c..0f451b3b6e1f 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -360,8 +360,8 @@ DEFINE_TYPES(pnv_core_infos)
>
> #define P9X_EX_NCU_SPEC_BAR 0x11010
>
> -static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr,
> - unsigned int width)
> +static uint64_t pnv_quad_power9_xscom_read(void *opaque, hwaddr addr,
> + unsigned int width)
> {
> uint32_t offset = addr >> 3;
> uint64_t val = -1;
> @@ -372,15 +372,15 @@ static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr,
> val = 0;
> break;
> default:
> - qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
> + qemu_log_mask(LOG_UNIMP, "%s: reading @0x%08x\n", __func__,
> offset);
> }
>
> return val;
> }
>
> -static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val,
> - unsigned int width)
> +static void pnv_quad_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val,
> + unsigned int width)
> {
> uint32_t offset = addr >> 3;
>
> @@ -394,9 +394,9 @@ static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val,
> }
> }
>
> -static const MemoryRegionOps pnv_quad_xscom_ops = {
> - .read = pnv_quad_xscom_read,
> - .write = pnv_quad_xscom_write,
> +static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
> + .read = pnv_quad_power9_xscom_read,
> + .write = pnv_quad_power9_xscom_write,
> .valid.min_access_size = 8,
> .valid.max_access_size = 8,
> .impl.min_access_size = 8,
> @@ -410,7 +410,8 @@ static void pnv_quad_realize(DeviceState *dev, Error **errp)
> char name[32];
>
> snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id);
> - pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops,
> + pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev),
> + &pnv_quad_power9_xscom_ops,
> eq, name, PNV9_XSCOM_EQ_SIZE);
> }
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 2/5] ppc/pnv: Subclass quad xscom callbacks
2023-07-04 5:41 [PATCH v2 0/5] ppc/pnv: Extend "quad" model for p10 Joel Stanley
2023-07-04 5:42 ` [PATCH v2 1/5] ppc/pnv: quad xscom callbacks are P9 specific Joel Stanley
@ 2023-07-04 5:42 ` Joel Stanley
2023-07-04 9:59 ` Frederic Barrat
2023-07-04 5:42 ` [PATCH v2 3/5] ppc/pnv: Add P10 quad xscom model Joel Stanley
` (4 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Joel Stanley @ 2023-07-04 5:42 UTC (permalink / raw)
To: Cédric Le Goater, Nicholas Piggin, Frédéric Barrat
Cc: qemu-devel, qemu-ppc
Make the existing pnv_quad_xscom_read/write be P9 specific, in
preparation for a different P10 callback.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
v2: Add scom region size to class
---
include/hw/ppc/pnv_core.h | 13 ++++++++++++-
hw/ppc/pnv.c | 11 +++++++----
hw/ppc/pnv_core.c | 40 ++++++++++++++++++++++++++-------------
3 files changed, 46 insertions(+), 18 deletions(-)
diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h
index 3d75706e95da..77ef00f47a72 100644
--- a/include/hw/ppc/pnv_core.h
+++ b/include/hw/ppc/pnv_core.h
@@ -60,8 +60,19 @@ static inline PnvCPUState *pnv_cpu_state(PowerPCCPU *cpu)
return (PnvCPUState *)cpu->machine_data;
}
+struct PnvQuadClass {
+ DeviceClass parent_class;
+
+ const MemoryRegionOps *xscom_ops;
+ uint64_t xscom_size;
+};
+
#define TYPE_PNV_QUAD "powernv-cpu-quad"
-OBJECT_DECLARE_SIMPLE_TYPE(PnvQuad, PNV_QUAD)
+
+#define PNV_QUAD_TYPE_SUFFIX "-" TYPE_PNV_QUAD
+#define PNV_QUAD_TYPE_NAME(cpu_model) cpu_model PNV_QUAD_TYPE_SUFFIX
+
+OBJECT_DECLARE_TYPE(PnvQuad, PnvQuadClass, PNV_QUAD)
struct PnvQuad {
DeviceState parent_obj;
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index fc083173f346..c77fdb6747a4 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1429,14 +1429,15 @@ static void pnv_chip_power9_instance_init(Object *obj)
}
static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq,
- PnvCore *pnv_core)
+ PnvCore *pnv_core,
+ const char *type)
{
char eq_name[32];
int core_id = CPU_CORE(pnv_core)->core_id;
snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
- sizeof(*eq), TYPE_PNV_QUAD,
+ sizeof(*eq), type,
&error_fatal, NULL);
object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
@@ -1454,7 +1455,8 @@ static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
for (i = 0; i < chip9->nr_quads; i++) {
PnvQuad *eq = &chip9->quads[i];
- pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
+ pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
+ PNV_QUAD_TYPE_NAME("power9"));
pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id),
&eq->xscom_regs);
@@ -1666,7 +1668,8 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
for (i = 0; i < chip10->nr_quads; i++) {
PnvQuad *eq = &chip10->quads[i];
- pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
+ pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
+ PNV_QUAD_TYPE_NAME("power9"));
pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
&eq->xscom_regs);
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 0f451b3b6e1f..73d25409c937 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -407,12 +407,14 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
static void pnv_quad_realize(DeviceState *dev, Error **errp)
{
PnvQuad *eq = PNV_QUAD(dev);
+ PnvQuadClass *pqc = PNV_QUAD_GET_CLASS(eq);
char name[32];
snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id);
pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev),
- &pnv_quad_power9_xscom_ops,
- eq, name, PNV9_XSCOM_EQ_SIZE);
+ pqc->xscom_ops,
+ eq, name,
+ pqc->xscom_size);
}
static Property pnv_quad_properties[] = {
@@ -420,6 +422,14 @@ static Property pnv_quad_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+static void pnv_quad_power9_class_init(ObjectClass *oc, void *data)
+{
+ PnvQuadClass *pqc = PNV_QUAD_CLASS(oc);
+
+ pqc->xscom_ops = &pnv_quad_power9_xscom_ops;
+ pqc->xscom_size = PNV9_XSCOM_EQ_SIZE;
+}
+
static void pnv_quad_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -429,16 +439,20 @@ static void pnv_quad_class_init(ObjectClass *oc, void *data)
dc->user_creatable = false;
}
-static const TypeInfo pnv_quad_info = {
- .name = TYPE_PNV_QUAD,
- .parent = TYPE_DEVICE,
- .instance_size = sizeof(PnvQuad),
- .class_init = pnv_quad_class_init,
+static const TypeInfo pnv_quad_infos[] = {
+ {
+ .name = TYPE_PNV_QUAD,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(PnvQuad),
+ .class_size = sizeof(PnvQuadClass),
+ .class_init = pnv_quad_class_init,
+ .abstract = true,
+ },
+ {
+ .parent = TYPE_PNV_QUAD,
+ .name = PNV_QUAD_TYPE_NAME("power9"),
+ .class_init = pnv_quad_power9_class_init,
+ },
};
-static void pnv_core_register_types(void)
-{
- type_register_static(&pnv_quad_info);
-}
-
-type_init(pnv_core_register_types)
+DEFINE_TYPES(pnv_quad_infos);
--
2.40.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v2 2/5] ppc/pnv: Subclass quad xscom callbacks
2023-07-04 5:42 ` [PATCH v2 2/5] ppc/pnv: Subclass quad xscom callbacks Joel Stanley
@ 2023-07-04 9:59 ` Frederic Barrat
0 siblings, 0 replies; 15+ messages in thread
From: Frederic Barrat @ 2023-07-04 9:59 UTC (permalink / raw)
To: Joel Stanley, Cédric Le Goater, Nicholas Piggin; +Cc: qemu-devel, qemu-ppc
On 04/07/2023 07:42, Joel Stanley wrote:
> Make the existing pnv_quad_xscom_read/write be P9 specific, in
> preparation for a different P10 callback.
>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Fred
> v2: Add scom region size to class
> ---
> include/hw/ppc/pnv_core.h | 13 ++++++++++++-
> hw/ppc/pnv.c | 11 +++++++----
> hw/ppc/pnv_core.c | 40 ++++++++++++++++++++++++++-------------
> 3 files changed, 46 insertions(+), 18 deletions(-)
>
> diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h
> index 3d75706e95da..77ef00f47a72 100644
> --- a/include/hw/ppc/pnv_core.h
> +++ b/include/hw/ppc/pnv_core.h
> @@ -60,8 +60,19 @@ static inline PnvCPUState *pnv_cpu_state(PowerPCCPU *cpu)
> return (PnvCPUState *)cpu->machine_data;
> }
>
> +struct PnvQuadClass {
> + DeviceClass parent_class;
> +
> + const MemoryRegionOps *xscom_ops;
> + uint64_t xscom_size;
> +};
> +
> #define TYPE_PNV_QUAD "powernv-cpu-quad"
> -OBJECT_DECLARE_SIMPLE_TYPE(PnvQuad, PNV_QUAD)
> +
> +#define PNV_QUAD_TYPE_SUFFIX "-" TYPE_PNV_QUAD
> +#define PNV_QUAD_TYPE_NAME(cpu_model) cpu_model PNV_QUAD_TYPE_SUFFIX
> +
> +OBJECT_DECLARE_TYPE(PnvQuad, PnvQuadClass, PNV_QUAD)
>
> struct PnvQuad {
> DeviceState parent_obj;
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index fc083173f346..c77fdb6747a4 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -1429,14 +1429,15 @@ static void pnv_chip_power9_instance_init(Object *obj)
> }
>
> static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq,
> - PnvCore *pnv_core)
> + PnvCore *pnv_core,
> + const char *type)
> {
> char eq_name[32];
> int core_id = CPU_CORE(pnv_core)->core_id;
>
> snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
> object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
> - sizeof(*eq), TYPE_PNV_QUAD,
> + sizeof(*eq), type,
> &error_fatal, NULL);
>
> object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
> @@ -1454,7 +1455,8 @@ static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
> for (i = 0; i < chip9->nr_quads; i++) {
> PnvQuad *eq = &chip9->quads[i];
>
> - pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
> + pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
> + PNV_QUAD_TYPE_NAME("power9"));
>
> pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id),
> &eq->xscom_regs);
> @@ -1666,7 +1668,8 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
> for (i = 0; i < chip10->nr_quads; i++) {
> PnvQuad *eq = &chip10->quads[i];
>
> - pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
> + pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
> + PNV_QUAD_TYPE_NAME("power9"));
>
> pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
> &eq->xscom_regs);
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index 0f451b3b6e1f..73d25409c937 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -407,12 +407,14 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
> static void pnv_quad_realize(DeviceState *dev, Error **errp)
> {
> PnvQuad *eq = PNV_QUAD(dev);
> + PnvQuadClass *pqc = PNV_QUAD_GET_CLASS(eq);
> char name[32];
>
> snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id);
> pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev),
> - &pnv_quad_power9_xscom_ops,
> - eq, name, PNV9_XSCOM_EQ_SIZE);
> + pqc->xscom_ops,
> + eq, name,
> + pqc->xscom_size);
> }
>
> static Property pnv_quad_properties[] = {
> @@ -420,6 +422,14 @@ static Property pnv_quad_properties[] = {
> DEFINE_PROP_END_OF_LIST(),
> };
>
> +static void pnv_quad_power9_class_init(ObjectClass *oc, void *data)
> +{
> + PnvQuadClass *pqc = PNV_QUAD_CLASS(oc);
> +
> + pqc->xscom_ops = &pnv_quad_power9_xscom_ops;
> + pqc->xscom_size = PNV9_XSCOM_EQ_SIZE;
> +}
> +
> static void pnv_quad_class_init(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
> @@ -429,16 +439,20 @@ static void pnv_quad_class_init(ObjectClass *oc, void *data)
> dc->user_creatable = false;
> }
>
> -static const TypeInfo pnv_quad_info = {
> - .name = TYPE_PNV_QUAD,
> - .parent = TYPE_DEVICE,
> - .instance_size = sizeof(PnvQuad),
> - .class_init = pnv_quad_class_init,
> +static const TypeInfo pnv_quad_infos[] = {
> + {
> + .name = TYPE_PNV_QUAD,
> + .parent = TYPE_DEVICE,
> + .instance_size = sizeof(PnvQuad),
> + .class_size = sizeof(PnvQuadClass),
> + .class_init = pnv_quad_class_init,
> + .abstract = true,
> + },
> + {
> + .parent = TYPE_PNV_QUAD,
> + .name = PNV_QUAD_TYPE_NAME("power9"),
> + .class_init = pnv_quad_power9_class_init,
> + },
> };
>
> -static void pnv_core_register_types(void)
> -{
> - type_register_static(&pnv_quad_info);
> -}
> -
> -type_init(pnv_core_register_types)
> +DEFINE_TYPES(pnv_quad_infos);
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 3/5] ppc/pnv: Add P10 quad xscom model
2023-07-04 5:41 [PATCH v2 0/5] ppc/pnv: Extend "quad" model for p10 Joel Stanley
2023-07-04 5:42 ` [PATCH v2 1/5] ppc/pnv: quad xscom callbacks are P9 specific Joel Stanley
2023-07-04 5:42 ` [PATCH v2 2/5] ppc/pnv: Subclass quad xscom callbacks Joel Stanley
@ 2023-07-04 5:42 ` Joel Stanley
2023-07-04 6:55 ` Cédric Le Goater
2023-07-04 10:11 ` Frederic Barrat
2023-07-04 5:42 ` [PATCH v2 4/5] ppc/pnv: Add P10 core " Joel Stanley
` (3 subsequent siblings)
6 siblings, 2 replies; 15+ messages in thread
From: Joel Stanley @ 2023-07-04 5:42 UTC (permalink / raw)
To: Cédric Le Goater, Nicholas Piggin, Frédéric Barrat
Cc: qemu-devel, qemu-ppc
Add a PnvQuad class for the P10 powernv machine. No xscoms are
implemented yet, but this allows them to be added.
The size is reduced to avoid the quad region from overlapping with the
core region.
address-space: xscom-0
0000000000000000-00000003ffffffff (prio 0, i/o): xscom-0
0000000100000000-00000001000fffff (prio 0, i/o): xscom-quad.0
0000000100108000-0000000100907fff (prio 0, i/o): xscom-core.3
0000000100110000-000000010090ffff (prio 0, i/o): xscom-core.2
0000000100120000-000000010091ffff (prio 0, i/o): xscom-core.1
0000000100140000-000000010093ffff (prio 0, i/o): xscom-core.0
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
v2: Fix unimp read message
Wrap lines at 80 col
Set size
---
include/hw/ppc/pnv_xscom.h | 2 +-
hw/ppc/pnv.c | 2 +-
hw/ppc/pnv_core.c | 54 ++++++++++++++++++++++++++++++++++++++
3 files changed, 56 insertions(+), 2 deletions(-)
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index cbe848d27ba0..f7da9a1dc617 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -129,7 +129,7 @@ struct PnvXScomInterfaceClass {
#define PNV10_XSCOM_EQ_BASE(core) \
((uint64_t) PNV10_XSCOM_EQ(PNV10_XSCOM_EQ_CHIPLET(core)))
-#define PNV10_XSCOM_EQ_SIZE 0x100000
+#define PNV10_XSCOM_EQ_SIZE 0x20000
#define PNV10_XSCOM_EC_BASE(core) \
((uint64_t) PNV10_XSCOM_EQ_BASE(core) | PNV10_XSCOM_EC(core & 0x3))
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index c77fdb6747a4..5f25fe985ab2 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1669,7 +1669,7 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
PnvQuad *eq = &chip10->quads[i];
pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
- PNV_QUAD_TYPE_NAME("power9"));
+ PNV_QUAD_TYPE_NAME("power10"));
pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
&eq->xscom_regs);
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 73d25409c937..e4df435b15e9 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -404,6 +404,47 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
+/*
+ * POWER10 Quads
+ */
+
+static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
+ unsigned int width)
+{
+ uint32_t offset = addr >> 3;
+ uint64_t val = -1;
+
+ switch (offset) {
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: reading @0x%08x\n", __func__,
+ offset);
+ }
+
+ return val;
+}
+
+static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned int width)
+{
+ uint32_t offset = addr >> 3;
+
+ switch (offset) {
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
+ offset);
+ }
+}
+
+static const MemoryRegionOps pnv_quad_power10_xscom_ops = {
+ .read = pnv_quad_power10_xscom_read,
+ .write = pnv_quad_power10_xscom_write,
+ .valid.min_access_size = 8,
+ .valid.max_access_size = 8,
+ .impl.min_access_size = 8,
+ .impl.max_access_size = 8,
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
static void pnv_quad_realize(DeviceState *dev, Error **errp)
{
PnvQuad *eq = PNV_QUAD(dev);
@@ -430,6 +471,14 @@ static void pnv_quad_power9_class_init(ObjectClass *oc, void *data)
pqc->xscom_size = PNV9_XSCOM_EQ_SIZE;
}
+static void pnv_quad_power10_class_init(ObjectClass *oc, void *data)
+{
+ PnvQuadClass *pqc = PNV_QUAD_CLASS(oc);
+
+ pqc->xscom_ops = &pnv_quad_power10_xscom_ops;
+ pqc->xscom_size = PNV10_XSCOM_EQ_SIZE;
+}
+
static void pnv_quad_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -453,6 +502,11 @@ static const TypeInfo pnv_quad_infos[] = {
.name = PNV_QUAD_TYPE_NAME("power9"),
.class_init = pnv_quad_power9_class_init,
},
+ {
+ .parent = TYPE_PNV_QUAD,
+ .name = PNV_QUAD_TYPE_NAME("power10"),
+ .class_init = pnv_quad_power10_class_init,
+ },
};
DEFINE_TYPES(pnv_quad_infos);
--
2.40.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v2 3/5] ppc/pnv: Add P10 quad xscom model
2023-07-04 5:42 ` [PATCH v2 3/5] ppc/pnv: Add P10 quad xscom model Joel Stanley
@ 2023-07-04 6:55 ` Cédric Le Goater
2023-07-04 10:11 ` Frederic Barrat
1 sibling, 0 replies; 15+ messages in thread
From: Cédric Le Goater @ 2023-07-04 6:55 UTC (permalink / raw)
To: Joel Stanley, Nicholas Piggin, Frédéric Barrat
Cc: qemu-devel, qemu-ppc
On 7/4/23 07:42, Joel Stanley wrote:
> Add a PnvQuad class for the P10 powernv machine. No xscoms are
> implemented yet, but this allows them to be added.
>
> The size is reduced to avoid the quad region from overlapping with the
> core region.
>
> address-space: xscom-0
> 0000000000000000-00000003ffffffff (prio 0, i/o): xscom-0
> 0000000100000000-00000001000fffff (prio 0, i/o): xscom-quad.0
> 0000000100108000-0000000100907fff (prio 0, i/o): xscom-core.3
> 0000000100110000-000000010090ffff (prio 0, i/o): xscom-core.2
> 0000000100120000-000000010091ffff (prio 0, i/o): xscom-core.1
> 0000000100140000-000000010093ffff (prio 0, i/o): xscom-core.0
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> v2: Fix unimp read message
> Wrap lines at 80 col
> Set size
> ---
> include/hw/ppc/pnv_xscom.h | 2 +-
> hw/ppc/pnv.c | 2 +-
> hw/ppc/pnv_core.c | 54 ++++++++++++++++++++++++++++++++++++++
> 3 files changed, 56 insertions(+), 2 deletions(-)
>
> diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
> index cbe848d27ba0..f7da9a1dc617 100644
> --- a/include/hw/ppc/pnv_xscom.h
> +++ b/include/hw/ppc/pnv_xscom.h
> @@ -129,7 +129,7 @@ struct PnvXScomInterfaceClass {
>
> #define PNV10_XSCOM_EQ_BASE(core) \
> ((uint64_t) PNV10_XSCOM_EQ(PNV10_XSCOM_EQ_CHIPLET(core)))
> -#define PNV10_XSCOM_EQ_SIZE 0x100000
> +#define PNV10_XSCOM_EQ_SIZE 0x20000
>
> #define PNV10_XSCOM_EC_BASE(core) \
> ((uint64_t) PNV10_XSCOM_EQ_BASE(core) | PNV10_XSCOM_EC(core & 0x3))
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index c77fdb6747a4..5f25fe985ab2 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -1669,7 +1669,7 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
> PnvQuad *eq = &chip10->quads[i];
>
> pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
> - PNV_QUAD_TYPE_NAME("power9"));
> + PNV_QUAD_TYPE_NAME("power10"));
>
> pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
> &eq->xscom_regs);
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index 73d25409c937..e4df435b15e9 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -404,6 +404,47 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
> .endianness = DEVICE_BIG_ENDIAN,
> };
>
> +/*
> + * POWER10 Quads
> + */
> +
> +static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
> + unsigned int width)
> +{
> + uint32_t offset = addr >> 3;
> + uint64_t val = -1;
> +
> + switch (offset) {
> + default:
> + qemu_log_mask(LOG_UNIMP, "%s: reading @0x%08x\n", __func__,
> + offset);
> + }
> +
> + return val;
> +}
> +
> +static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr,
> + uint64_t val, unsigned int width)
> +{
> + uint32_t offset = addr >> 3;
> +
> + switch (offset) {
> + default:
> + qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
> + offset);
> + }
> +}
> +
> +static const MemoryRegionOps pnv_quad_power10_xscom_ops = {
> + .read = pnv_quad_power10_xscom_read,
> + .write = pnv_quad_power10_xscom_write,
> + .valid.min_access_size = 8,
> + .valid.max_access_size = 8,
> + .impl.min_access_size = 8,
> + .impl.max_access_size = 8,
> + .endianness = DEVICE_BIG_ENDIAN,
> +};
> +
> static void pnv_quad_realize(DeviceState *dev, Error **errp)
> {
> PnvQuad *eq = PNV_QUAD(dev);
> @@ -430,6 +471,14 @@ static void pnv_quad_power9_class_init(ObjectClass *oc, void *data)
> pqc->xscom_size = PNV9_XSCOM_EQ_SIZE;
> }
>
> +static void pnv_quad_power10_class_init(ObjectClass *oc, void *data)
> +{
> + PnvQuadClass *pqc = PNV_QUAD_CLASS(oc);
> +
> + pqc->xscom_ops = &pnv_quad_power10_xscom_ops;
> + pqc->xscom_size = PNV10_XSCOM_EQ_SIZE;
> +}
> +
> static void pnv_quad_class_init(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
> @@ -453,6 +502,11 @@ static const TypeInfo pnv_quad_infos[] = {
> .name = PNV_QUAD_TYPE_NAME("power9"),
> .class_init = pnv_quad_power9_class_init,
> },
> + {
> + .parent = TYPE_PNV_QUAD,
> + .name = PNV_QUAD_TYPE_NAME("power10"),
> + .class_init = pnv_quad_power10_class_init,
> + },
> };
>
> DEFINE_TYPES(pnv_quad_infos);
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v2 3/5] ppc/pnv: Add P10 quad xscom model
2023-07-04 5:42 ` [PATCH v2 3/5] ppc/pnv: Add P10 quad xscom model Joel Stanley
2023-07-04 6:55 ` Cédric Le Goater
@ 2023-07-04 10:11 ` Frederic Barrat
1 sibling, 0 replies; 15+ messages in thread
From: Frederic Barrat @ 2023-07-04 10:11 UTC (permalink / raw)
To: Joel Stanley, Cédric Le Goater, Nicholas Piggin; +Cc: qemu-devel, qemu-ppc
On 04/07/2023 07:42, Joel Stanley wrote:
> Add a PnvQuad class for the P10 powernv machine. No xscoms are
> implemented yet, but this allows them to be added.
>
> The size is reduced to avoid the quad region from overlapping with the
> core region.
>
> address-space: xscom-0
> 0000000000000000-00000003ffffffff (prio 0, i/o): xscom-0
> 0000000100000000-00000001000fffff (prio 0, i/o): xscom-quad.0
> 0000000100108000-0000000100907fff (prio 0, i/o): xscom-core.3
> 0000000100110000-000000010090ffff (prio 0, i/o): xscom-core.2
> 0000000100120000-000000010091ffff (prio 0, i/o): xscom-core.1
> 0000000100140000-000000010093ffff (prio 0, i/o): xscom-core.0
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Fred
> v2: Fix unimp read message
> Wrap lines at 80 col
> Set size
> ---
> include/hw/ppc/pnv_xscom.h | 2 +-
> hw/ppc/pnv.c | 2 +-
> hw/ppc/pnv_core.c | 54 ++++++++++++++++++++++++++++++++++++++
> 3 files changed, 56 insertions(+), 2 deletions(-)
>
> diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
> index cbe848d27ba0..f7da9a1dc617 100644
> --- a/include/hw/ppc/pnv_xscom.h
> +++ b/include/hw/ppc/pnv_xscom.h
> @@ -129,7 +129,7 @@ struct PnvXScomInterfaceClass {
>
> #define PNV10_XSCOM_EQ_BASE(core) \
> ((uint64_t) PNV10_XSCOM_EQ(PNV10_XSCOM_EQ_CHIPLET(core)))
> -#define PNV10_XSCOM_EQ_SIZE 0x100000
> +#define PNV10_XSCOM_EQ_SIZE 0x20000
>
> #define PNV10_XSCOM_EC_BASE(core) \
> ((uint64_t) PNV10_XSCOM_EQ_BASE(core) | PNV10_XSCOM_EC(core & 0x3))
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index c77fdb6747a4..5f25fe985ab2 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -1669,7 +1669,7 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
> PnvQuad *eq = &chip10->quads[i];
>
> pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
> - PNV_QUAD_TYPE_NAME("power9"));
> + PNV_QUAD_TYPE_NAME("power10"));
>
> pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
> &eq->xscom_regs);
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index 73d25409c937..e4df435b15e9 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -404,6 +404,47 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
> .endianness = DEVICE_BIG_ENDIAN,
> };
>
> +/*
> + * POWER10 Quads
> + */
> +
> +static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
> + unsigned int width)
> +{
> + uint32_t offset = addr >> 3;
> + uint64_t val = -1;
> +
> + switch (offset) {
> + default:
> + qemu_log_mask(LOG_UNIMP, "%s: reading @0x%08x\n", __func__,
> + offset);
> + }
> +
> + return val;
> +}
> +
> +static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr,
> + uint64_t val, unsigned int width)
> +{
> + uint32_t offset = addr >> 3;
> +
> + switch (offset) {
> + default:
> + qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
> + offset);
> + }
> +}
> +
> +static const MemoryRegionOps pnv_quad_power10_xscom_ops = {
> + .read = pnv_quad_power10_xscom_read,
> + .write = pnv_quad_power10_xscom_write,
> + .valid.min_access_size = 8,
> + .valid.max_access_size = 8,
> + .impl.min_access_size = 8,
> + .impl.max_access_size = 8,
> + .endianness = DEVICE_BIG_ENDIAN,
> +};
> +
> static void pnv_quad_realize(DeviceState *dev, Error **errp)
> {
> PnvQuad *eq = PNV_QUAD(dev);
> @@ -430,6 +471,14 @@ static void pnv_quad_power9_class_init(ObjectClass *oc, void *data)
> pqc->xscom_size = PNV9_XSCOM_EQ_SIZE;
> }
>
> +static void pnv_quad_power10_class_init(ObjectClass *oc, void *data)
> +{
> + PnvQuadClass *pqc = PNV_QUAD_CLASS(oc);
> +
> + pqc->xscom_ops = &pnv_quad_power10_xscom_ops;
> + pqc->xscom_size = PNV10_XSCOM_EQ_SIZE;
> +}
> +
> static void pnv_quad_class_init(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
> @@ -453,6 +502,11 @@ static const TypeInfo pnv_quad_infos[] = {
> .name = PNV_QUAD_TYPE_NAME("power9"),
> .class_init = pnv_quad_power9_class_init,
> },
> + {
> + .parent = TYPE_PNV_QUAD,
> + .name = PNV_QUAD_TYPE_NAME("power10"),
> + .class_init = pnv_quad_power10_class_init,
> + },
> };
>
> DEFINE_TYPES(pnv_quad_infos);
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 4/5] ppc/pnv: Add P10 core xscom model
2023-07-04 5:41 [PATCH v2 0/5] ppc/pnv: Extend "quad" model for p10 Joel Stanley
` (2 preceding siblings ...)
2023-07-04 5:42 ` [PATCH v2 3/5] ppc/pnv: Add P10 quad xscom model Joel Stanley
@ 2023-07-04 5:42 ` Joel Stanley
2023-07-04 6:55 ` Cédric Le Goater
2023-07-04 10:12 ` Frederic Barrat
2023-07-04 5:42 ` [PATCH v2 5/5] ppc/pnv: Return zero for core thread state xscom Joel Stanley
` (2 subsequent siblings)
6 siblings, 2 replies; 15+ messages in thread
From: Joel Stanley @ 2023-07-04 5:42 UTC (permalink / raw)
To: Cédric Le Goater, Nicholas Piggin, Frédéric Barrat
Cc: qemu-devel, qemu-ppc
Like the quad xscoms, add a core model for P10 to allow future
differentiation from P9.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
hw/ppc/pnv_core.c | 44 ++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 42 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index e4df435b15e9..1eec28c88c41 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -167,6 +167,47 @@ static const MemoryRegionOps pnv_core_power9_xscom_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
+/*
+ * POWER10 core controls
+ */
+
+static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr,
+ unsigned int width)
+{
+ uint32_t offset = addr >> 3;
+ uint64_t val = 0;
+
+ switch (offset) {
+ default:
+ qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
+ addr);
+ }
+
+ return val;
+}
+
+static void pnv_core_power10_xscom_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned int width)
+{
+ uint32_t offset = addr >> 3;
+
+ switch (offset) {
+ default:
+ qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
+ addr);
+ }
+}
+
+static const MemoryRegionOps pnv_core_power10_xscom_ops = {
+ .read = pnv_core_power10_xscom_read,
+ .write = pnv_core_power10_xscom_write,
+ .valid.min_access_size = 8,
+ .valid.max_access_size = 8,
+ .impl.min_access_size = 8,
+ .impl.max_access_size = 8,
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp)
{
CPUPPCState *env = &cpu->env;
@@ -315,8 +356,7 @@ static void pnv_core_power10_class_init(ObjectClass *oc, void *data)
{
PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
- /* TODO: Use the P9 XSCOMs for now on P10 */
- pcc->xscom_ops = &pnv_core_power9_xscom_ops;
+ pcc->xscom_ops = &pnv_core_power10_xscom_ops;
}
static void pnv_core_class_init(ObjectClass *oc, void *data)
--
2.40.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v2 4/5] ppc/pnv: Add P10 core xscom model
2023-07-04 5:42 ` [PATCH v2 4/5] ppc/pnv: Add P10 core " Joel Stanley
@ 2023-07-04 6:55 ` Cédric Le Goater
2023-07-04 10:12 ` Frederic Barrat
1 sibling, 0 replies; 15+ messages in thread
From: Cédric Le Goater @ 2023-07-04 6:55 UTC (permalink / raw)
To: Joel Stanley, Nicholas Piggin, Frédéric Barrat
Cc: qemu-devel, qemu-ppc
On 7/4/23 07:42, Joel Stanley wrote:
> Like the quad xscoms, add a core model for P10 to allow future
> differentiation from P9.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/ppc/pnv_core.c | 44 ++++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 42 insertions(+), 2 deletions(-)
>
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index e4df435b15e9..1eec28c88c41 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -167,6 +167,47 @@ static const MemoryRegionOps pnv_core_power9_xscom_ops = {
> .endianness = DEVICE_BIG_ENDIAN,
> };
>
> +/*
> + * POWER10 core controls
> + */
> +
> +static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr,
> + unsigned int width)
> +{
> + uint32_t offset = addr >> 3;
> + uint64_t val = 0;
> +
> + switch (offset) {
> + default:
> + qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
> + addr);
> + }
> +
> + return val;
> +}
> +
> +static void pnv_core_power10_xscom_write(void *opaque, hwaddr addr,
> + uint64_t val, unsigned int width)
> +{
> + uint32_t offset = addr >> 3;
> +
> + switch (offset) {
> + default:
> + qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
> + addr);
> + }
> +}
> +
> +static const MemoryRegionOps pnv_core_power10_xscom_ops = {
> + .read = pnv_core_power10_xscom_read,
> + .write = pnv_core_power10_xscom_write,
> + .valid.min_access_size = 8,
> + .valid.max_access_size = 8,
> + .impl.min_access_size = 8,
> + .impl.max_access_size = 8,
> + .endianness = DEVICE_BIG_ENDIAN,
> +};
> +
> static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp)
> {
> CPUPPCState *env = &cpu->env;
> @@ -315,8 +356,7 @@ static void pnv_core_power10_class_init(ObjectClass *oc, void *data)
> {
> PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
>
> - /* TODO: Use the P9 XSCOMs for now on P10 */
> - pcc->xscom_ops = &pnv_core_power9_xscom_ops;
> + pcc->xscom_ops = &pnv_core_power10_xscom_ops;
> }
>
> static void pnv_core_class_init(ObjectClass *oc, void *data)
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v2 4/5] ppc/pnv: Add P10 core xscom model
2023-07-04 5:42 ` [PATCH v2 4/5] ppc/pnv: Add P10 core " Joel Stanley
2023-07-04 6:55 ` Cédric Le Goater
@ 2023-07-04 10:12 ` Frederic Barrat
1 sibling, 0 replies; 15+ messages in thread
From: Frederic Barrat @ 2023-07-04 10:12 UTC (permalink / raw)
To: Joel Stanley, Cédric Le Goater, Nicholas Piggin; +Cc: qemu-devel, qemu-ppc
On 04/07/2023 07:42, Joel Stanley wrote:
> Like the quad xscoms, add a core model for P10 to allow future
> differentiation from P9.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Fred
> hw/ppc/pnv_core.c | 44 ++++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 42 insertions(+), 2 deletions(-)
>
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index e4df435b15e9..1eec28c88c41 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -167,6 +167,47 @@ static const MemoryRegionOps pnv_core_power9_xscom_ops = {
> .endianness = DEVICE_BIG_ENDIAN,
> };
>
> +/*
> + * POWER10 core controls
> + */
> +
> +static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr,
> + unsigned int width)
> +{
> + uint32_t offset = addr >> 3;
> + uint64_t val = 0;
> +
> + switch (offset) {
> + default:
> + qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
> + addr);
> + }
> +
> + return val;
> +}
> +
> +static void pnv_core_power10_xscom_write(void *opaque, hwaddr addr,
> + uint64_t val, unsigned int width)
> +{
> + uint32_t offset = addr >> 3;
> +
> + switch (offset) {
> + default:
> + qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
> + addr);
> + }
> +}
> +
> +static const MemoryRegionOps pnv_core_power10_xscom_ops = {
> + .read = pnv_core_power10_xscom_read,
> + .write = pnv_core_power10_xscom_write,
> + .valid.min_access_size = 8,
> + .valid.max_access_size = 8,
> + .impl.min_access_size = 8,
> + .impl.max_access_size = 8,
> + .endianness = DEVICE_BIG_ENDIAN,
> +};
> +
> static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp)
> {
> CPUPPCState *env = &cpu->env;
> @@ -315,8 +356,7 @@ static void pnv_core_power10_class_init(ObjectClass *oc, void *data)
> {
> PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
>
> - /* TODO: Use the P9 XSCOMs for now on P10 */
> - pcc->xscom_ops = &pnv_core_power9_xscom_ops;
> + pcc->xscom_ops = &pnv_core_power10_xscom_ops;
> }
>
> static void pnv_core_class_init(ObjectClass *oc, void *data)
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 5/5] ppc/pnv: Return zero for core thread state xscom
2023-07-04 5:41 [PATCH v2 0/5] ppc/pnv: Extend "quad" model for p10 Joel Stanley
` (3 preceding siblings ...)
2023-07-04 5:42 ` [PATCH v2 4/5] ppc/pnv: Add P10 core " Joel Stanley
@ 2023-07-04 5:42 ` Joel Stanley
2023-07-04 10:12 ` Frederic Barrat
2023-07-04 23:12 ` [PATCH v2 0/5] ppc/pnv: Extend "quad" model for p10 Daniel Henrique Barboza
2023-07-05 1:15 ` Nicholas Piggin
6 siblings, 1 reply; 15+ messages in thread
From: Joel Stanley @ 2023-07-04 5:42 UTC (permalink / raw)
To: Cédric Le Goater, Nicholas Piggin, Frédéric Barrat
Cc: qemu-devel, qemu-ppc
Firmware now warns if booting in LPAR per core mode (PPC bit 62). So
this warning doesn't trigger, report the core thread state is 0.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
hw/ppc/pnv_core.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 1eec28c88c41..b7223bb44597 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -116,6 +116,8 @@ static const MemoryRegionOps pnv_core_power8_xscom_ops = {
#define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d
#define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a
+#define PNV9_XSCOM_EC_CORE_THREAD_STATE 0x10ab3
+
static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr,
unsigned int width)
{
@@ -134,6 +136,9 @@ static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr,
case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
val = 0x0;
break;
+ case PNV9_XSCOM_EC_CORE_THREAD_STATE:
+ val = 0;
+ break;
default:
qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
addr);
@@ -171,6 +176,8 @@ static const MemoryRegionOps pnv_core_power9_xscom_ops = {
* POWER10 core controls
*/
+#define PNV10_XSCOM_EC_CORE_THREAD_STATE 0x412
+
static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr,
unsigned int width)
{
@@ -178,6 +185,9 @@ static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr,
uint64_t val = 0;
switch (offset) {
+ case PNV10_XSCOM_EC_CORE_THREAD_STATE:
+ val = 0;
+ break;
default:
qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
addr);
--
2.40.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v2 5/5] ppc/pnv: Return zero for core thread state xscom
2023-07-04 5:42 ` [PATCH v2 5/5] ppc/pnv: Return zero for core thread state xscom Joel Stanley
@ 2023-07-04 10:12 ` Frederic Barrat
0 siblings, 0 replies; 15+ messages in thread
From: Frederic Barrat @ 2023-07-04 10:12 UTC (permalink / raw)
To: Joel Stanley, Cédric Le Goater, Nicholas Piggin; +Cc: qemu-devel, qemu-ppc
On 04/07/2023 07:42, Joel Stanley wrote:
> Firmware now warns if booting in LPAR per core mode (PPC bit 62). So
> this warning doesn't trigger, report the core thread state is 0.
>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Fred
> hw/ppc/pnv_core.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index 1eec28c88c41..b7223bb44597 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -116,6 +116,8 @@ static const MemoryRegionOps pnv_core_power8_xscom_ops = {
> #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d
> #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a
>
> +#define PNV9_XSCOM_EC_CORE_THREAD_STATE 0x10ab3
> +
> static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr,
> unsigned int width)
> {
> @@ -134,6 +136,9 @@ static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr,
> case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
> val = 0x0;
> break;
> + case PNV9_XSCOM_EC_CORE_THREAD_STATE:
> + val = 0;
> + break;
> default:
> qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
> addr);
> @@ -171,6 +176,8 @@ static const MemoryRegionOps pnv_core_power9_xscom_ops = {
> * POWER10 core controls
> */
>
> +#define PNV10_XSCOM_EC_CORE_THREAD_STATE 0x412
> +
> static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr,
> unsigned int width)
> {
> @@ -178,6 +185,9 @@ static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr,
> uint64_t val = 0;
>
> switch (offset) {
> + case PNV10_XSCOM_EC_CORE_THREAD_STATE:
> + val = 0;
> + break;
> default:
> qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
> addr);
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 0/5] ppc/pnv: Extend "quad" model for p10
2023-07-04 5:41 [PATCH v2 0/5] ppc/pnv: Extend "quad" model for p10 Joel Stanley
` (4 preceding siblings ...)
2023-07-04 5:42 ` [PATCH v2 5/5] ppc/pnv: Return zero for core thread state xscom Joel Stanley
@ 2023-07-04 23:12 ` Daniel Henrique Barboza
2023-07-05 1:15 ` Nicholas Piggin
6 siblings, 0 replies; 15+ messages in thread
From: Daniel Henrique Barboza @ 2023-07-04 23:12 UTC (permalink / raw)
To: Joel Stanley, Cédric Le Goater, Nicholas Piggin,
Frédéric Barrat
Cc: qemu-devel, qemu-ppc
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
On 7/4/23 02:41, Joel Stanley wrote:
> The quad model implements the EC xscoms for the p9 machine, reusing the
> same model for p10 which isn't quite correct. This series adds a PnvQuad
> class and subclasses it for P9 and P10.
>
> I mistakenly thought we needed the quad model to implement the core
> thread state scom on p10, because the read was coming in to the address
> belonging to the quad. In fact the quad region was too large,
> overlapping with the core. This is fixed in v2, and the core thread is
> back where it should be in the core model. This should address Nick's
> feedback on the v1 cover letter.
>
> v2 also adds Cedric's r-b, fixes the s/write/read/ mistakes, and is
> checkpatch clean.
>
> v1: https://lore.kernel.org/qemu-devel/20230630035547.80329-1-joel@jms.id.au/
>
> Joel Stanley (5):
> ppc/pnv: quad xscom callbacks are P9 specific
> ppc/pnv: Subclass quad xscom callbacks
> ppc/pnv: Add P10 quad xscom model
> ppc/pnv: Add P10 core xscom model
> ppc/pnv: Return zero for core thread state xscom
>
> include/hw/ppc/pnv_core.h | 13 ++-
> include/hw/ppc/pnv_xscom.h | 2 +-
> hw/ppc/pnv.c | 11 ++-
> hw/ppc/pnv_core.c | 165 +++++++++++++++++++++++++++++++------
> 4 files changed, 162 insertions(+), 29 deletions(-)
>
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v2 0/5] ppc/pnv: Extend "quad" model for p10
2023-07-04 5:41 [PATCH v2 0/5] ppc/pnv: Extend "quad" model for p10 Joel Stanley
` (5 preceding siblings ...)
2023-07-04 23:12 ` [PATCH v2 0/5] ppc/pnv: Extend "quad" model for p10 Daniel Henrique Barboza
@ 2023-07-05 1:15 ` Nicholas Piggin
6 siblings, 0 replies; 15+ messages in thread
From: Nicholas Piggin @ 2023-07-05 1:15 UTC (permalink / raw)
To: Joel Stanley, Cédric Le Goater, Frédéric Barrat
Cc: qemu-devel, qemu-ppc
On Tue Jul 4, 2023 at 3:41 PM AEST, Joel Stanley wrote:
> The quad model implements the EC xscoms for the p9 machine, reusing the
> same model for p10 which isn't quite correct. This series adds a PnvQuad
> class and subclasses it for P9 and P10.
>
> I mistakenly thought we needed the quad model to implement the core
> thread state scom on p10, because the read was coming in to the address
> belonging to the quad. In fact the quad region was too large,
> overlapping with the core. This is fixed in v2, and the core thread is
> back where it should be in the core model. This should address Nick's
> feedback on the v1 cover letter.
Already queued, but FWIW these all look good to me. Thanks, this is a
good base to add some more functions on too.
One thing is the core xscom regions seem to still overlap...
Thanks,
Nick
>
> v2 also adds Cedric's r-b, fixes the s/write/read/ mistakes, and is
> checkpatch clean.
>
> v1: https://lore.kernel.org/qemu-devel/20230630035547.80329-1-joel@jms.id.au/
>
> Joel Stanley (5):
> ppc/pnv: quad xscom callbacks are P9 specific
> ppc/pnv: Subclass quad xscom callbacks
> ppc/pnv: Add P10 quad xscom model
> ppc/pnv: Add P10 core xscom model
> ppc/pnv: Return zero for core thread state xscom
>
> include/hw/ppc/pnv_core.h | 13 ++-
> include/hw/ppc/pnv_xscom.h | 2 +-
> hw/ppc/pnv.c | 11 ++-
> hw/ppc/pnv_core.c | 165 +++++++++++++++++++++++++++++++------
> 4 files changed, 162 insertions(+), 29 deletions(-)
^ permalink raw reply [flat|nested] 15+ messages in thread