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[213.175.37.10]) by smtp.gmail.com with ESMTPSA id w6-20020a17090633c600b0098748422178sm13193720eja.56.2023.07.04.07.20.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 07:20:22 -0700 (PDT) Date: Tue, 4 Jul 2023 16:20:21 +0200 From: Igor Mammedov To: Akihiko Odaki Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, Ani Sinha , "Michael S . Tsirkin" , Marcel Apfelbaum , Sriram Yagnaraman , Jason Wang , Keith Busch , Klaus Jensen Subject: Re: [PATCH v4 2/2] pcie: Specify 0 for ARI next function numbers Message-ID: <20230704162021.18e05471@imammedo.users.ipa.redhat.com> In-Reply-To: <20230704122215.23270-3-akihiko.odaki@daynix.com> References: <20230704122215.23270-1-akihiko.odaki@daynix.com> <20230704122215.23270-3-akihiko.odaki@daynix.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, 4 Jul 2023 21:22:14 +0900 Akihiko Odaki wrote: > The current implementers of ARI are all SR-IOV devices. The ARI next > function number field is undefined for VF . ^ add a reference to a spec (spec name, rev, chapter) where it's declared so reviewer or whoever reads it later could easily find relevant documentation. >The PF should end the linked > list formed with the field by specifying 0. ditto > > For migration, the field will keep having 1 as its value on the old > virt models. > > Fixes: 2503461691 ("pcie: Add some SR/IOV API documentation in docs/pcie_sriov.txt") > Fixes: 44c2c09488 ("hw/nvme: Add support for SR-IOV") > Fixes: 3a977deebe ("Intrdocue igb device emulation") > Signed-off-by: Akihiko Odaki > --- > include/hw/pci/pci.h | 2 ++ > hw/core/machine.c | 1 + > hw/pci/pci.c | 2 ++ > hw/pci/pcie.c | 2 +- > 4 files changed, 6 insertions(+), 1 deletion(-) > > diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h > index e6d0574a29..9c5b5eb206 100644 > --- a/include/hw/pci/pci.h > +++ b/include/hw/pci/pci.h > @@ -209,6 +209,8 @@ enum { > QEMU_PCIE_CAP_CXL = (1 << QEMU_PCIE_CXL_BITNR), > #define QEMU_PCIE_ERR_UNC_MASK_BITNR 11 > QEMU_PCIE_ERR_UNC_MASK = (1 << QEMU_PCIE_ERR_UNC_MASK_BITNR), > +#define QEMU_PCIE_ARI_NEXTFN_1_BITNR 12 > + QEMU_PCIE_ARI_NEXTFN_1 = (1 << QEMU_PCIE_ARI_NEXTFN_1_BITNR), > }; > > typedef struct PCIINTxRoute { > diff --git a/hw/core/machine.c b/hw/core/machine.c > index 46f8f9a2b0..f0d35c6401 100644 > --- a/hw/core/machine.c > +++ b/hw/core/machine.c > @@ -41,6 +41,7 @@ > > GlobalProperty hw_compat_8_0[] = { > { "migration", "multifd-flush-after-each-section", "on"}, > + { TYPE_PCI_DEVICE, "x-pcie-ari-nextfn-1", "on" }, > }; > const size_t hw_compat_8_0_len = G_N_ELEMENTS(hw_compat_8_0); > > diff --git a/hw/pci/pci.c b/hw/pci/pci.c > index e2eb4c3b4a..45a9bc0da8 100644 > --- a/hw/pci/pci.c > +++ b/hw/pci/pci.c > @@ -82,6 +82,8 @@ static Property pci_props[] = { > DEFINE_PROP_UINT32("acpi-index", PCIDevice, acpi_index, 0), > DEFINE_PROP_BIT("x-pcie-err-unc-mask", PCIDevice, cap_present, > QEMU_PCIE_ERR_UNC_MASK_BITNR, true), > + DEFINE_PROP_BIT("x-pcie-ari-nextfn-1", PCIDevice, cap_present, > + QEMU_PCIE_ARI_NEXTFN_1_BITNR, false), > DEFINE_PROP_END_OF_LIST() > }; > > diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c > index 9a3f6430e8..cf09e03a10 100644 > --- a/hw/pci/pcie.c > +++ b/hw/pci/pcie.c > @@ -1030,7 +1030,7 @@ void pcie_sync_bridge_lnk(PCIDevice *bridge_dev) > /* ARI */ > void pcie_ari_init(PCIDevice *dev, uint16_t offset) > { > - uint16_t nextfn = 1; > + uint16_t nextfn = dev->cap_present & QEMU_PCIE_ARI_NEXTFN_1 ? 1 : 0; > > pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER, > offset, PCI_ARI_SIZEOF);