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From: Conor Dooley <conor@kernel.org>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
	alistair.francis@wdc.com, bmeng@tinylab.org,
	liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com,
	palmer@rivosinc.com, ajones@ventanamicro.com,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: Re: [PATCH v8 02/20] hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set
Date: Wed, 5 Jul 2023 22:49:22 +0100	[thread overview]
Message-ID: <20230705-gallstone-untitled-1463e43aa33c@spud> (raw)
In-Reply-To: <20230705213955.429895-3-dbarboza@ventanamicro.com>

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On Wed, Jul 05, 2023 at 06:39:37PM -0300, Daniel Henrique Barboza wrote:
> The absence of a satp mode in riscv_host_cpu_init() is causing the
> following error:
> 
> $ ./qemu/build/qemu-system-riscv64  -machine virt,accel=kvm \
>     -m 2G -smp 1  -nographic -snapshot \
>     -kernel ./guest_imgs/Image \
>     -initrd ./guest_imgs/rootfs_kvm_riscv64.img \
>     -append "earlycon=sbi root=/dev/ram rw" \
>     -cpu host
> **
> ERROR:../target/riscv/cpu.c:320:satp_mode_str: code should not be
> reached
> Bail out! ERROR:../target/riscv/cpu.c:320:satp_mode_str: code should
> not be reached
> Aborted
> 
> The error is triggered from create_fdt_socket_cpus() in hw/riscv/virt.c.
> It's trying to get satp_mode_str for a NULL cpu->cfg.satp_mode.map.
> 
> For this KVM cpu we would need to inherit the satp supported modes
> from the RISC-V host. At this moment this is not possible because the
> KVM driver does not support it. And even when it does we can't just let
> this broken for every other older kernel.
> 
> Since mmu-type is not a required node, according to [1], skip the
> 'mmu-type' FDT node if there's no satp_mode set. We'll revisit this
> logic when we can get satp information from KVM.
> 
> [1] https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/cpu.yaml

I don't think this is the correct link to reference as backup, as the
generic binding sets out no requirements. I think you would want to link
to the RISC-V specific cpus binding.

That said, things like FreeBSD and U-Boot appear to require mmu-type
https://lore.kernel.org/all/20230705-fondue-bagginess-66c25f1a4135@spud/
so I am wondering if we should in fact make the mmu-type a required
property in the RISC-V specific binding.

Since nommu is covered by an mmu type of "riscv,none", I am kinda
struggling to think of a case where it should be left out (while
describing real hardware at least).

Cheers,
Conor.

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  reply	other threads:[~2023-07-05 21:50 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-05 21:39 [PATCH v8 00/20] target/riscv, KVM: fixes and enhancements Daniel Henrique Barboza
2023-07-05 21:39 ` [PATCH v8 01/20] target/riscv: skip features setup for KVM CPUs Daniel Henrique Barboza
2023-07-05 21:39 ` [PATCH v8 02/20] hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set Daniel Henrique Barboza
2023-07-05 21:49   ` Conor Dooley [this message]
2023-07-05 22:00     ` Daniel Henrique Barboza
2023-07-05 22:12       ` Conor Dooley
2023-07-05 22:18         ` Daniel Henrique Barboza
2023-07-05 21:39 ` [PATCH v8 03/20] target/riscv/cpu.c: restrict 'mvendorid' value Daniel Henrique Barboza
2023-07-05 21:39 ` [PATCH v8 04/20] target/riscv/cpu.c: restrict 'mimpid' value Daniel Henrique Barboza
2023-07-05 21:39 ` [PATCH v8 05/20] target/riscv/cpu.c: restrict 'marchid' value Daniel Henrique Barboza
2023-07-05 21:39 ` [PATCH v8 06/20] target/riscv: use KVM scratch CPUs to init KVM properties Daniel Henrique Barboza
2023-07-05 21:39 ` [PATCH v8 07/20] target/riscv: read marchid/mimpid in kvm_riscv_init_machine_ids() Daniel Henrique Barboza
2023-07-05 21:39 ` [PATCH v8 08/20] target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs Daniel Henrique Barboza
2023-07-05 21:39 ` [PATCH v8 09/20] linux-headers: Update to v6.4-rc1 Daniel Henrique Barboza
2023-07-05 21:39 ` [PATCH v8 10/20] target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPU Daniel Henrique Barboza
2023-07-05 21:39 ` [PATCH v8 11/20] target/riscv/cpu: add misa_ext_info_arr[] Daniel Henrique Barboza
2023-07-05 21:39 ` [PATCH v8 12/20] target/riscv: add KVM specific MISA properties Daniel Henrique Barboza
2023-07-05 21:39 ` [PATCH v8 13/20] target/riscv/kvm.c: update KVM MISA bits Daniel Henrique Barboza
2023-07-05 21:39 ` [PATCH v8 14/20] target/riscv/kvm.c: add multi-letter extension KVM properties Daniel Henrique Barboza
2023-07-06  8:45   ` Andrew Jones
2023-07-06  9:37     ` Andrew Jones
2023-07-05 21:39 ` [PATCH v8 15/20] target/riscv/cpu.c: add satp_mode properties earlier Daniel Henrique Barboza
2023-07-05 21:39 ` [PATCH v8 16/20] target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext() Daniel Henrique Barboza
2023-07-05 21:39 ` [PATCH v8 17/20] target/riscv/cpu.c: create KVM mock properties Daniel Henrique Barboza
2023-07-05 21:39 ` [PATCH v8 18/20] target/riscv: update multi-letter extension KVM properties Daniel Henrique Barboza
2023-07-05 21:39 ` [PATCH v8 19/20] target/riscv/kvm.c: add kvmconfig_get_cfg_addr() helper Daniel Henrique Barboza
2023-07-05 21:39 ` [PATCH v8 20/20] target/riscv/kvm.c: read/write (cbom|cboz)_blocksize in KVM Daniel Henrique Barboza

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