[PATCH] pnv/xive: Print CPU target in all TIMA traces

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* [PATCH] pnv/xive: Print CPU target in all TIMA traces
@ 2023-07-05 11:00 Frederic Barrat
  2023-07-05 11:12 ` Philippe Mathieu-Daudé
                   ` (2 more replies)
  0 siblings, 3 replies; 7+ messages in thread
From: Frederic Barrat @ 2023-07-05 11:00 UTC (permalink / raw)
  To: Cédric Le Goater, Daniel Henrique Barboza, qemu-ppc,
	qemu-devel

Add the CPU target in the trace when reading/writing the TIMA
space. It was already done for other TIMA ops (notify, accept, ...),
only missing for those 2. Useful for debug and even more now that we
experiment with SMT.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
---
 hw/intc/trace-events | 4 ++--
 hw/intc/xive.c       | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 5c6094c457..36ff71f947 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -265,8 +265,8 @@ xive_source_esb_read(uint64_t addr, uint32_t srcno, uint64_t value) "@0x%"PRIx64
 xive_source_esb_write(uint64_t addr, uint32_t srcno, uint64_t value) "@0x%"PRIx64" IRQ 0x%x val=0x%"PRIx64
 xive_router_end_notify(uint8_t end_blk, uint32_t end_idx, uint32_t end_data) "END 0x%02x/0x%04x -> enqueue 0x%08x"
 xive_router_end_escalate(uint8_t end_blk, uint32_t end_idx, uint8_t esc_blk, uint32_t esc_idx, uint32_t end_data) "END 0x%02x/0x%04x -> escalate END 0x%02x/0x%04x data 0x%08x"
-xive_tctx_tm_write(uint64_t offset, unsigned int size, uint64_t value) "@0x%"PRIx64" sz=%d val=0x%" PRIx64
-xive_tctx_tm_read(uint64_t offset, unsigned int size, uint64_t value) "@0x%"PRIx64" sz=%d val=0x%" PRIx64
+xive_tctx_tm_write(uint32_t index, uint64_t offset, unsigned int size, uint64_t value) "target=%d @0x%"PRIx64" sz=%d val=0x%" PRIx64
+xive_tctx_tm_read(uint32_t index, uint64_t offset, unsigned int size, uint64_t value) "target=%d @0x%"PRIx64" sz=%d val=0x%" PRIx64
 xive_presenter_notify(uint8_t nvt_blk, uint32_t nvt_idx, uint8_t ring) "found NVT 0x%x/0x%x ring=0x%x"
 xive_end_source_read(uint8_t end_blk, uint32_t end_idx, uint64_t addr) "END 0x%x/0x%x @0x%"PRIx64
 
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index c014e961a4..56670b2cac 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -566,7 +566,7 @@ void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
 {
     const XiveTmOp *xto;
 
-    trace_xive_tctx_tm_write(offset, size, value);
+    trace_xive_tctx_tm_write(tctx->cs->cpu_index, offset, size, value);
 
     /*
      * TODO: check V bit in Q[0-3]W2
@@ -639,7 +639,7 @@ uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
      */
     ret = xive_tm_raw_read(tctx, offset, size);
 out:
-    trace_xive_tctx_tm_read(offset, size, ret);
+    trace_xive_tctx_tm_read(tctx->cs->cpu_index, offset, size, ret);
     return ret;
 }
 
-- 
2.41.0



^ permalink raw reply related	[flat|nested] 7+ messages in thread

* Re: [PATCH] pnv/xive: Print CPU target in all TIMA traces
  2023-07-05 11:00 [PATCH] pnv/xive: Print CPU target in all TIMA traces Frederic Barrat
@ 2023-07-05 11:12 ` Philippe Mathieu-Daudé
  2023-07-05 11:18   ` Cédric Le Goater
  2023-07-05 11:14 ` Cédric Le Goater
  2023-07-05 17:04 ` Daniel Henrique Barboza
  2 siblings, 1 reply; 7+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-07-05 11:12 UTC (permalink / raw)
  To: Frederic Barrat, Cédric Le Goater, Daniel Henrique Barboza,
	qemu-ppc, qemu-devel

On 5/7/23 13:00, Frederic Barrat wrote:
> Add the CPU target in the trace when reading/writing the TIMA
> space. It was already done for other TIMA ops (notify, accept, ...),
> only missing for those 2. Useful for debug and even more now that we
> experiment with SMT.
> 
> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
> ---
>   hw/intc/trace-events | 4 ++--
>   hw/intc/xive.c       | 4 ++--
>   2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/hw/intc/trace-events b/hw/intc/trace-events
> index 5c6094c457..36ff71f947 100644
> --- a/hw/intc/trace-events
> +++ b/hw/intc/trace-events
> @@ -265,8 +265,8 @@ xive_source_esb_read(uint64_t addr, uint32_t srcno, uint64_t value) "@0x%"PRIx64
>   xive_source_esb_write(uint64_t addr, uint32_t srcno, uint64_t value) "@0x%"PRIx64" IRQ 0x%x val=0x%"PRIx64
>   xive_router_end_notify(uint8_t end_blk, uint32_t end_idx, uint32_t end_data) "END 0x%02x/0x%04x -> enqueue 0x%08x"
>   xive_router_end_escalate(uint8_t end_blk, uint32_t end_idx, uint8_t esc_blk, uint32_t esc_idx, uint32_t end_data) "END 0x%02x/0x%04x -> escalate END 0x%02x/0x%04x data 0x%08x"
> -xive_tctx_tm_write(uint64_t offset, unsigned int size, uint64_t value) "@0x%"PRIx64" sz=%d val=0x%" PRIx64
> -xive_tctx_tm_read(uint64_t offset, unsigned int size, uint64_t value) "@0x%"PRIx64" sz=%d val=0x%" PRIx64
> +xive_tctx_tm_write(uint32_t index, uint64_t offset, unsigned int size, uint64_t value) "target=%d @0x%"PRIx64" sz=%d val=0x%" PRIx64
> +xive_tctx_tm_read(uint32_t index, uint64_t offset, unsigned int size, uint64_t value) "target=%d @0x%"PRIx64" sz=%d val=0x%" PRIx64

"target" is kinda confusing, what about:

xive_tctx_tm_read(uint32_t cpu_index, ...) "cpu=%d @0x%"PRIx64" ...

?


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] pnv/xive: Print CPU target in all TIMA traces
  2023-07-05 11:12 ` Philippe Mathieu-Daudé
@ 2023-07-05 11:18   ` Cédric Le Goater
  2023-07-05 11:26     ` Philippe Mathieu-Daudé
  0 siblings, 1 reply; 7+ messages in thread
From: Cédric Le Goater @ 2023-07-05 11:18 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, Frederic Barrat,
	Daniel Henrique Barboza, qemu-ppc, qemu-devel

On 7/5/23 13:12, Philippe Mathieu-Daudé wrote:
> On 5/7/23 13:00, Frederic Barrat wrote:
>> Add the CPU target in the trace when reading/writing the TIMA
>> space. It was already done for other TIMA ops (notify, accept, ...),
>> only missing for those 2. Useful for debug and even more now that we
>> experiment with SMT.
>>
>> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
>> ---
>>   hw/intc/trace-events | 4 ++--
>>   hw/intc/xive.c       | 4 ++--
>>   2 files changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/hw/intc/trace-events b/hw/intc/trace-events
>> index 5c6094c457..36ff71f947 100644
>> --- a/hw/intc/trace-events
>> +++ b/hw/intc/trace-events
>> @@ -265,8 +265,8 @@ xive_source_esb_read(uint64_t addr, uint32_t srcno, uint64_t value) "@0x%"PRIx64
>>   xive_source_esb_write(uint64_t addr, uint32_t srcno, uint64_t value) "@0x%"PRIx64" IRQ 0x%x val=0x%"PRIx64
>>   xive_router_end_notify(uint8_t end_blk, uint32_t end_idx, uint32_t end_data) "END 0x%02x/0x%04x -> enqueue 0x%08x"
>>   xive_router_end_escalate(uint8_t end_blk, uint32_t end_idx, uint8_t esc_blk, uint32_t esc_idx, uint32_t end_data) "END 0x%02x/0x%04x -> escalate END 0x%02x/0x%04x data 0x%08x"
>> -xive_tctx_tm_write(uint64_t offset, unsigned int size, uint64_t value) "@0x%"PRIx64" sz=%d val=0x%" PRIx64
>> -xive_tctx_tm_read(uint64_t offset, unsigned int size, uint64_t value) "@0x%"PRIx64" sz=%d val=0x%" PRIx64
>> +xive_tctx_tm_write(uint32_t index, uint64_t offset, unsigned int size, uint64_t value) "target=%d @0x%"PRIx64" sz=%d val=0x%" PRIx64
>> +xive_tctx_tm_read(uint32_t index, uint64_t offset, unsigned int size, uint64_t value) "target=%d @0x%"PRIx64" sz=%d val=0x%" PRIx64
> 
> "target" is kinda confusing, what about:
> 
> xive_tctx_tm_read(uint32_t cpu_index, ...) "cpu=%d @0x%"PRIx64" ...

An interrupt 'source' is served by a 'target', a target could be a CPU,
a vCPU id, a group of vCPU, a process id.

'target' is part of the XIVE nomenclature, in HW specs, in drivers, FW,
Linux, KVM, and models in QEMU. It is fine.

Thanks,

C.
  
> 
> ?



^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] pnv/xive: Print CPU target in all TIMA traces
  2023-07-05 11:18   ` Cédric Le Goater
@ 2023-07-05 11:26     ` Philippe Mathieu-Daudé
  2023-07-05 11:46       ` Cédric Le Goater
  0 siblings, 1 reply; 7+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-07-05 11:26 UTC (permalink / raw)
  To: Cédric Le Goater, Frederic Barrat, Daniel Henrique Barboza,
	qemu-ppc, qemu-devel

On 5/7/23 13:18, Cédric Le Goater wrote:
> On 7/5/23 13:12, Philippe Mathieu-Daudé wrote:
>> On 5/7/23 13:00, Frederic Barrat wrote:
>>> Add the CPU target in the trace when reading/writing the TIMA
>>> space. It was already done for other TIMA ops (notify, accept, ...),
>>> only missing for those 2. Useful for debug and even more now that we
>>> experiment with SMT.
>>>
>>> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
>>> ---
>>>   hw/intc/trace-events | 4 ++--
>>>   hw/intc/xive.c       | 4 ++--
>>>   2 files changed, 4 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/hw/intc/trace-events b/hw/intc/trace-events
>>> index 5c6094c457..36ff71f947 100644
>>> --- a/hw/intc/trace-events
>>> +++ b/hw/intc/trace-events
>>> @@ -265,8 +265,8 @@ xive_source_esb_read(uint64_t addr, uint32_t 
>>> srcno, uint64_t value) "@0x%"PRIx64
>>>   xive_source_esb_write(uint64_t addr, uint32_t srcno, uint64_t 
>>> value) "@0x%"PRIx64" IRQ 0x%x val=0x%"PRIx64
>>>   xive_router_end_notify(uint8_t end_blk, uint32_t end_idx, uint32_t 
>>> end_data) "END 0x%02x/0x%04x -> enqueue 0x%08x"
>>>   xive_router_end_escalate(uint8_t end_blk, uint32_t end_idx, uint8_t 
>>> esc_blk, uint32_t esc_idx, uint32_t end_data) "END 0x%02x/0x%04x -> 
>>> escalate END 0x%02x/0x%04x data 0x%08x"
>>> -xive_tctx_tm_write(uint64_t offset, unsigned int size, uint64_t 
>>> value) "@0x%"PRIx64" sz=%d val=0x%" PRIx64
>>> -xive_tctx_tm_read(uint64_t offset, unsigned int size, uint64_t 
>>> value) "@0x%"PRIx64" sz=%d val=0x%" PRIx64
>>> +xive_tctx_tm_write(uint32_t index, uint64_t offset, unsigned int 
>>> size, uint64_t value) "target=%d @0x%"PRIx64" sz=%d val=0x%" PRIx64
>>> +xive_tctx_tm_read(uint32_t index, uint64_t offset, unsigned int 
>>> size, uint64_t value) "target=%d @0x%"PRIx64" sz=%d val=0x%" PRIx64
>>
>> "target" is kinda confusing, what about:
>>
>> xive_tctx_tm_read(uint32_t cpu_index, ...) "cpu=%d @0x%"PRIx64" ...
> 
> An interrupt 'source' is served by a 'target', a target could be a CPU,
> a vCPU id, a group of vCPU, a process id.
> 
> 'target' is part of the XIVE nomenclature, in HW specs, in drivers, FW,
> Linux, KVM, and models in QEMU. It is fine.

Ah OK. Then xive_tctx_tm_read(uint32_t target, ...).



^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] pnv/xive: Print CPU target in all TIMA traces
  2023-07-05 11:26     ` Philippe Mathieu-Daudé
@ 2023-07-05 11:46       ` Cédric Le Goater
  0 siblings, 0 replies; 7+ messages in thread
From: Cédric Le Goater @ 2023-07-05 11:46 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, Frederic Barrat,
	Daniel Henrique Barboza, qemu-ppc, qemu-devel

On 7/5/23 13:26, Philippe Mathieu-Daudé wrote:
> On 5/7/23 13:18, Cédric Le Goater wrote:
>> On 7/5/23 13:12, Philippe Mathieu-Daudé wrote:
>>> On 5/7/23 13:00, Frederic Barrat wrote:
>>>> Add the CPU target in the trace when reading/writing the TIMA
>>>> space. It was already done for other TIMA ops (notify, accept, ...),
>>>> only missing for those 2. Useful for debug and even more now that we
>>>> experiment with SMT.
>>>>
>>>> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
>>>> ---
>>>>   hw/intc/trace-events | 4 ++--
>>>>   hw/intc/xive.c       | 4 ++--
>>>>   2 files changed, 4 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/hw/intc/trace-events b/hw/intc/trace-events
>>>> index 5c6094c457..36ff71f947 100644
>>>> --- a/hw/intc/trace-events
>>>> +++ b/hw/intc/trace-events
>>>> @@ -265,8 +265,8 @@ xive_source_esb_read(uint64_t addr, uint32_t srcno, uint64_t value) "@0x%"PRIx64
>>>>   xive_source_esb_write(uint64_t addr, uint32_t srcno, uint64_t value) "@0x%"PRIx64" IRQ 0x%x val=0x%"PRIx64
>>>>   xive_router_end_notify(uint8_t end_blk, uint32_t end_idx, uint32_t end_data) "END 0x%02x/0x%04x -> enqueue 0x%08x"
>>>>   xive_router_end_escalate(uint8_t end_blk, uint32_t end_idx, uint8_t esc_blk, uint32_t esc_idx, uint32_t end_data) "END 0x%02x/0x%04x -> escalate END 0x%02x/0x%04x data 0x%08x"
>>>> -xive_tctx_tm_write(uint64_t offset, unsigned int size, uint64_t value) "@0x%"PRIx64" sz=%d val=0x%" PRIx64
>>>> -xive_tctx_tm_read(uint64_t offset, unsigned int size, uint64_t value) "@0x%"PRIx64" sz=%d val=0x%" PRIx64
>>>> +xive_tctx_tm_write(uint32_t index, uint64_t offset, unsigned int size, uint64_t value) "target=%d @0x%"PRIx64" sz=%d val=0x%" PRIx64
>>>> +xive_tctx_tm_read(uint32_t index, uint64_t offset, unsigned int size, uint64_t value) "target=%d @0x%"PRIx64" sz=%d val=0x%" PRIx64
>>>
>>> "target" is kinda confusing, what about:
>>>
>>> xive_tctx_tm_read(uint32_t cpu_index, ...) "cpu=%d @0x%"PRIx64" ...
>>
>> An interrupt 'source' is served by a 'target', a target could be a CPU,
>> a vCPU id, a group of vCPU, a process id.
>>
>> 'target' is part of the XIVE nomenclature, in HW specs, in drivers, FW,
>> Linux, KVM, and models in QEMU. It is fine.
> 
> Ah OK. Then xive_tctx_tm_read(uint32_t target, ...).

better indeed. What would be good to know also, is which vCPU is currently
dispatched on the HW thread. The info is in W2 of the ring being accessed.

Thanks,

C.


  



^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] pnv/xive: Print CPU target in all TIMA traces
  2023-07-05 11:00 [PATCH] pnv/xive: Print CPU target in all TIMA traces Frederic Barrat
  2023-07-05 11:12 ` Philippe Mathieu-Daudé
@ 2023-07-05 11:14 ` Cédric Le Goater
  2023-07-05 17:04 ` Daniel Henrique Barboza
  2 siblings, 0 replies; 7+ messages in thread
From: Cédric Le Goater @ 2023-07-05 11:14 UTC (permalink / raw)
  To: Frederic Barrat, Daniel Henrique Barboza, qemu-ppc, qemu-devel

On 7/5/23 13:00, Frederic Barrat wrote:
> Add the CPU target in the trace when reading/writing the TIMA
> space. It was already done for other TIMA ops (notify, accept, ...),
> only missing for those 2. Useful for debug and even more now that we
> experiment with SMT.
> 
> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>


Reviewed-by: Cédric Le Goater <clg@kaod.org>

Thanks,

C.


> ---
>   hw/intc/trace-events | 4 ++--
>   hw/intc/xive.c       | 4 ++--
>   2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/hw/intc/trace-events b/hw/intc/trace-events
> index 5c6094c457..36ff71f947 100644
> --- a/hw/intc/trace-events
> +++ b/hw/intc/trace-events
> @@ -265,8 +265,8 @@ xive_source_esb_read(uint64_t addr, uint32_t srcno, uint64_t value) "@0x%"PRIx64
>   xive_source_esb_write(uint64_t addr, uint32_t srcno, uint64_t value) "@0x%"PRIx64" IRQ 0x%x val=0x%"PRIx64
>   xive_router_end_notify(uint8_t end_blk, uint32_t end_idx, uint32_t end_data) "END 0x%02x/0x%04x -> enqueue 0x%08x"
>   xive_router_end_escalate(uint8_t end_blk, uint32_t end_idx, uint8_t esc_blk, uint32_t esc_idx, uint32_t end_data) "END 0x%02x/0x%04x -> escalate END 0x%02x/0x%04x data 0x%08x"
> -xive_tctx_tm_write(uint64_t offset, unsigned int size, uint64_t value) "@0x%"PRIx64" sz=%d val=0x%" PRIx64
> -xive_tctx_tm_read(uint64_t offset, unsigned int size, uint64_t value) "@0x%"PRIx64" sz=%d val=0x%" PRIx64
> +xive_tctx_tm_write(uint32_t index, uint64_t offset, unsigned int size, uint64_t value) "target=%d @0x%"PRIx64" sz=%d val=0x%" PRIx64
> +xive_tctx_tm_read(uint32_t index, uint64_t offset, unsigned int size, uint64_t value) "target=%d @0x%"PRIx64" sz=%d val=0x%" PRIx64
>   xive_presenter_notify(uint8_t nvt_blk, uint32_t nvt_idx, uint8_t ring) "found NVT 0x%x/0x%x ring=0x%x"
>   xive_end_source_read(uint8_t end_blk, uint32_t end_idx, uint64_t addr) "END 0x%x/0x%x @0x%"PRIx64
>   
> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> index c014e961a4..56670b2cac 100644
> --- a/hw/intc/xive.c
> +++ b/hw/intc/xive.c
> @@ -566,7 +566,7 @@ void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
>   {
>       const XiveTmOp *xto;
>   
> -    trace_xive_tctx_tm_write(offset, size, value);
> +    trace_xive_tctx_tm_write(tctx->cs->cpu_index, offset, size, value);
>   
>       /*
>        * TODO: check V bit in Q[0-3]W2
> @@ -639,7 +639,7 @@ uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
>        */
>       ret = xive_tm_raw_read(tctx, offset, size);
>   out:
> -    trace_xive_tctx_tm_read(offset, size, ret);
> +    trace_xive_tctx_tm_read(tctx->cs->cpu_index, offset, size, ret);
>       return ret;
>   }
>   



^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] pnv/xive: Print CPU target in all TIMA traces
  2023-07-05 11:00 [PATCH] pnv/xive: Print CPU target in all TIMA traces Frederic Barrat
  2023-07-05 11:12 ` Philippe Mathieu-Daudé
  2023-07-05 11:14 ` Cédric Le Goater
@ 2023-07-05 17:04 ` Daniel Henrique Barboza
  2 siblings, 0 replies; 7+ messages in thread
From: Daniel Henrique Barboza @ 2023-07-05 17:04 UTC (permalink / raw)
  To: Frederic Barrat, Cédric Le Goater, qemu-ppc, qemu-devel

Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,


Daniel

On 7/5/23 08:00, Frederic Barrat wrote:
> Add the CPU target in the trace when reading/writing the TIMA
> space. It was already done for other TIMA ops (notify, accept, ...),
> only missing for those 2. Useful for debug and even more now that we
> experiment with SMT.
> 
> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
> ---
>   hw/intc/trace-events | 4 ++--
>   hw/intc/xive.c       | 4 ++--
>   2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/hw/intc/trace-events b/hw/intc/trace-events
> index 5c6094c457..36ff71f947 100644
> --- a/hw/intc/trace-events
> +++ b/hw/intc/trace-events
> @@ -265,8 +265,8 @@ xive_source_esb_read(uint64_t addr, uint32_t srcno, uint64_t value) "@0x%"PRIx64
>   xive_source_esb_write(uint64_t addr, uint32_t srcno, uint64_t value) "@0x%"PRIx64" IRQ 0x%x val=0x%"PRIx64
>   xive_router_end_notify(uint8_t end_blk, uint32_t end_idx, uint32_t end_data) "END 0x%02x/0x%04x -> enqueue 0x%08x"
>   xive_router_end_escalate(uint8_t end_blk, uint32_t end_idx, uint8_t esc_blk, uint32_t esc_idx, uint32_t end_data) "END 0x%02x/0x%04x -> escalate END 0x%02x/0x%04x data 0x%08x"
> -xive_tctx_tm_write(uint64_t offset, unsigned int size, uint64_t value) "@0x%"PRIx64" sz=%d val=0x%" PRIx64
> -xive_tctx_tm_read(uint64_t offset, unsigned int size, uint64_t value) "@0x%"PRIx64" sz=%d val=0x%" PRIx64
> +xive_tctx_tm_write(uint32_t index, uint64_t offset, unsigned int size, uint64_t value) "target=%d @0x%"PRIx64" sz=%d val=0x%" PRIx64
> +xive_tctx_tm_read(uint32_t index, uint64_t offset, unsigned int size, uint64_t value) "target=%d @0x%"PRIx64" sz=%d val=0x%" PRIx64
>   xive_presenter_notify(uint8_t nvt_blk, uint32_t nvt_idx, uint8_t ring) "found NVT 0x%x/0x%x ring=0x%x"
>   xive_end_source_read(uint8_t end_blk, uint32_t end_idx, uint64_t addr) "END 0x%x/0x%x @0x%"PRIx64
>   
> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> index c014e961a4..56670b2cac 100644
> --- a/hw/intc/xive.c
> +++ b/hw/intc/xive.c
> @@ -566,7 +566,7 @@ void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
>   {
>       const XiveTmOp *xto;
>   
> -    trace_xive_tctx_tm_write(offset, size, value);
> +    trace_xive_tctx_tm_write(tctx->cs->cpu_index, offset, size, value);
>   
>       /*
>        * TODO: check V bit in Q[0-3]W2
> @@ -639,7 +639,7 @@ uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
>        */
>       ret = xive_tm_raw_read(tctx, offset, size);
>   out:
> -    trace_xive_tctx_tm_read(offset, size, ret);
> +    trace_xive_tctx_tm_read(tctx->cs->cpu_index, offset, size, ret);
>       return ret;
>   }
>   


^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2023-07-05 17:05 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-07-05 11:00 [PATCH] pnv/xive: Print CPU target in all TIMA traces Frederic Barrat
2023-07-05 11:12 ` Philippe Mathieu-Daudé
2023-07-05 11:18   ` Cédric Le Goater
2023-07-05 11:26     ` Philippe Mathieu-Daudé
2023-07-05 11:46       ` Cédric Le Goater
2023-07-05 11:14 ` Cédric Le Goater
2023-07-05 17:04 ` Daniel Henrique Barboza

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