From: Tao Su <tao1.su@linux.intel.com>
To: qemu-devel@nongnu.org
Cc: pbonzini@redhat.com, imammedo@redhat.com, xiaoyao.li@intel.com,
lei4.wang@intel.com, qian.wen@intel.com, tao1.su@linux.intel.com
Subject: [PATCH v2 3/6] target/i386: Allow MCDT_NO if host supports
Date: Thu, 6 Jul 2023 13:49:46 +0800 [thread overview]
Message-ID: <20230706054949.66556-4-tao1.su@linux.intel.com> (raw)
In-Reply-To: <20230706054949.66556-1-tao1.su@linux.intel.com>
MCDT_NO bit indicates HW contains the security fix and doesn't need to
be mitigated to avoid data-dependent behaviour for certain instructions.
It needs no hypervisor support. Treat it as supported regardless of what
KVM reports.
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
---
target/i386/kvm/kvm.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index de531842f6..ebfaf3d24c 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -432,6 +432,10 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
uint32_t eax;
host_cpuid(7, 1, &eax, &unused, &unused, &unused);
ret |= eax & (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC);
+ } else if (function == 7 && index == 2 && reg == R_EDX) {
+ uint32_t edx;
+ host_cpuid(7, 2, &unused, &unused, &unused, &edx);
+ ret |= edx & CPUID_7_2_EDX_MCDT_NO;
} else if (function == 0xd && index == 0 &&
(reg == R_EAX || reg == R_EDX)) {
/*
--
2.34.1
next prev parent reply other threads:[~2023-07-06 5:51 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-06 5:49 [PATCH v2 0/6] Add new CPU model GraniteRapids Tao Su
2023-07-06 5:49 ` [PATCH v2 1/6] target/i386: Add FEAT_7_1_EDX to adjust feature level Tao Su
2023-07-06 5:49 ` [PATCH v2 2/6] target/i386: Add support for MCDT_NO in CPUID enumeration Tao Su
2023-07-06 5:49 ` Tao Su [this message]
2023-07-06 5:49 ` [PATCH v2 4/6] target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES Tao Su
2023-07-06 5:49 ` [PATCH v2 5/6] target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model Tao Su
2023-07-06 5:49 ` [PATCH v2 6/6] target/i386: Add new CPU model GraniteRapids Tao Su
2024-01-30 10:14 ` Igor Mammedov
2024-01-30 13:34 ` Tao Su
2024-01-31 12:34 ` Igor Mammedov
2024-01-31 13:01 ` Tao Su
2023-07-07 10:52 ` [PATCH v2 0/6] " Paolo Bonzini
2023-07-07 12:37 ` Tao Su
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230706054949.66556-4-tao1.su@linux.intel.com \
--to=tao1.su@linux.intel.com \
--cc=imammedo@redhat.com \
--cc=lei4.wang@intel.com \
--cc=pbonzini@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=qian.wen@intel.com \
--cc=xiaoyao.li@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).