From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 14/14] target/arm: Avoid over-length shift in arm_cpu_sve_finalize() error case
Date: Thu, 6 Jul 2023 14:25:12 +0100 [thread overview]
Message-ID: <20230706132512.3534397-15-peter.maydell@linaro.org> (raw)
In-Reply-To: <20230706132512.3534397-1-peter.maydell@linaro.org>
If you build QEMU with the clang sanitizer enabled, you can see it
fire when running the arm-cpu-features test:
$ QTEST_QEMU_BINARY=./build/arm-clang/qemu-system-aarch64 ./build/arm-clang/tests/qtest/arm-cpu-features
[...]
../../target/arm/cpu64.c:125:19: runtime error: shift exponent 64 is too large for 64-bit type 'unsigned long long'
[...]
This happens because the user can specify some incorrect SVE
properties that result in our calculating a max_vq of 0. We catch
this and error out, but before we do that we calculate
vq_mask = MAKE_64BIT_MASK(0, max_vq);$
and the MAKE_64BIT_MASK() call is only valid for lengths that are
greater than zero, so we hit the undefined behaviour.
Change the logic so that if max_vq is 0 we specifically set vq_mask
to 0 without going via MAKE_64BIT_MASK(). This lets us drop the
max_vq check from the error-exit logic, because if max_vq is 0 then
vq_map must now be 0.
The UB only happens in the case where the user passed us an incorrect
set of SVE properties, so it's not a big problem in practice.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230704154332.3014896-1-peter.maydell@linaro.org
---
target/arm/cpu64.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 6eaf8e32cfa..6012e4ef549 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -122,10 +122,10 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
vq = ctz32(tmp) + 1;
max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
- vq_mask = MAKE_64BIT_MASK(0, max_vq);
+ vq_mask = max_vq > 0 ? MAKE_64BIT_MASK(0, max_vq) : 0;
vq_map = vq_supported & ~vq_init & vq_mask;
- if (max_vq == 0 || vq_map == 0) {
+ if (vq_map == 0) {
error_setg(errp, "cannot disable sve%d", vq * 128);
error_append_hint(errp, "Disabling sve%d results in all "
"vector lengths being disabled.\n",
--
2.34.1
next prev parent reply other threads:[~2023-07-06 13:26 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-06 13:24 [PULL v2 00/14] target-arm queue Peter Maydell
2023-07-06 13:24 ` [PULL 01/14] target/arm: Add raw_writes ops for register whose write induce TLB maintenance Peter Maydell
2023-07-06 13:25 ` [PULL 02/14] hw/arm/sbsa-ref: use XHCI to replace EHCI Peter Maydell
2023-07-06 13:25 ` [PULL 03/14] tests/tcg/aarch64/sysregs.c: Use S syntax for id_aa64zfr0_el1 and id_aa64smfr0_el1 Peter Maydell
2023-07-06 13:25 ` [PULL 04/14] target/arm: Avoid splitting Zregs across lines in dump Peter Maydell
2023-07-06 13:25 ` [PULL 05/14] target/arm: Dump ZA[] when active Peter Maydell
2023-07-06 13:25 ` [PULL 06/14] target/arm: Fix SME full tile indexing Peter Maydell
2023-07-06 13:25 ` [PULL 07/14] target/arm: Handle IC IVAU to improve compatibility with JITs Peter Maydell
2023-07-06 13:25 ` [PULL 08/14] tests/qtest: xlnx-canfd-test: Fix code coverity issues Peter Maydell
2023-07-06 13:25 ` [PULL 09/14] target/arm: gdbstub: Guard M-profile code with CONFIG_TCG Peter Maydell
2023-07-06 13:25 ` [PULL 10/14] hw: arm: allwinner-sramc: Set class_size Peter Maydell
2023-07-06 13:25 ` [PULL 11/14] target/xtensa: Assert that interrupt level is within bounds Peter Maydell
2023-07-06 13:25 ` [PULL 12/14] target/arm: Suppress more TCG unimplemented features in ID registers Peter Maydell
2023-07-06 13:25 ` [PULL 13/14] target/arm: Define neoverse-v1 Peter Maydell
2023-07-06 13:25 ` Peter Maydell [this message]
2023-07-06 17:19 ` [PULL v2 00/14] target-arm queue Richard Henderson
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