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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 04/14] target/arm: Avoid splitting Zregs across lines in dump
Date: Thu,  6 Jul 2023 14:25:02 +0100	[thread overview]
Message-ID: <20230706132512.3534397-5-peter.maydell@linaro.org> (raw)
In-Reply-To: <20230706132512.3534397-1-peter.maydell@linaro.org>

From: Richard Henderson <richard.henderson@linaro.org>

Allow the line length to extend to 548 columns.  While annoyingly wide,
it's still less confusing than the continuations we print.  Also, the
default VL used by Linux (and max for A64FX) uses only 140 columns.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230622151201.1578522-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 36 ++++++++++++++----------------------
 1 file changed, 14 insertions(+), 22 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index a1e77698ba2..f12c714bc43 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -955,7 +955,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
     ARMCPU *cpu = ARM_CPU(cs);
     CPUARMState *env = &cpu->env;
     uint32_t psr = pstate_read(env);
-    int i;
+    int i, j;
     int el = arm_current_el(env);
     const char *ns_status;
     bool sve;
@@ -1014,7 +1014,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
     }
 
     if (sve) {
-        int j, zcr_len = sve_vqm1_for_el(env, el);
+        int zcr_len = sve_vqm1_for_el(env, el);
 
         for (i = 0; i <= FFR_PRED_NUM; i++) {
             bool eol;
@@ -1054,32 +1054,24 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
             }
         }
 
-        for (i = 0; i < 32; i++) {
-            if (zcr_len == 0) {
+        if (zcr_len == 0) {
+            /*
+             * With vl=16, there are only 37 columns per register,
+             * so output two registers per line.
+             */
+            for (i = 0; i < 32; i++) {
                 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
                              i, env->vfp.zregs[i].d[1],
                              env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
-            } else if (zcr_len == 1) {
-                qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
-                             ":%016" PRIx64 ":%016" PRIx64 "\n",
-                             i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
-                             env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
-            } else {
+            }
+        } else {
+            for (i = 0; i < 32; i++) {
+                qemu_fprintf(f, "Z%02d=", i);
                 for (j = zcr_len; j >= 0; j--) {
-                    bool odd = (zcr_len - j) % 2 != 0;
-                    if (j == zcr_len) {
-                        qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
-                    } else if (!odd) {
-                        if (j > 0) {
-                            qemu_fprintf(f, "   [%x-%x]=", j, j - 1);
-                        } else {
-                            qemu_fprintf(f, "     [%x]=", j);
-                        }
-                    }
                     qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
                                  env->vfp.zregs[i].d[j * 2 + 1],
-                                 env->vfp.zregs[i].d[j * 2],
-                                 odd || j == 0 ? "\n" : ":");
+                                 env->vfp.zregs[i].d[j * 2 + 0],
+                                 j ? ":" : "\n");
                 }
             }
         }
-- 
2.34.1



  parent reply	other threads:[~2023-07-06 13:27 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-06 13:24 [PULL v2 00/14] target-arm queue Peter Maydell
2023-07-06 13:24 ` [PULL 01/14] target/arm: Add raw_writes ops for register whose write induce TLB maintenance Peter Maydell
2023-07-06 13:25 ` [PULL 02/14] hw/arm/sbsa-ref: use XHCI to replace EHCI Peter Maydell
2023-07-06 13:25 ` [PULL 03/14] tests/tcg/aarch64/sysregs.c: Use S syntax for id_aa64zfr0_el1 and id_aa64smfr0_el1 Peter Maydell
2023-07-06 13:25 ` Peter Maydell [this message]
2023-07-06 13:25 ` [PULL 05/14] target/arm: Dump ZA[] when active Peter Maydell
2023-07-06 13:25 ` [PULL 06/14] target/arm: Fix SME full tile indexing Peter Maydell
2023-07-06 13:25 ` [PULL 07/14] target/arm: Handle IC IVAU to improve compatibility with JITs Peter Maydell
2023-07-06 13:25 ` [PULL 08/14] tests/qtest: xlnx-canfd-test: Fix code coverity issues Peter Maydell
2023-07-06 13:25 ` [PULL 09/14] target/arm: gdbstub: Guard M-profile code with CONFIG_TCG Peter Maydell
2023-07-06 13:25 ` [PULL 10/14] hw: arm: allwinner-sramc: Set class_size Peter Maydell
2023-07-06 13:25 ` [PULL 11/14] target/xtensa: Assert that interrupt level is within bounds Peter Maydell
2023-07-06 13:25 ` [PULL 12/14] target/arm: Suppress more TCG unimplemented features in ID registers Peter Maydell
2023-07-06 13:25 ` [PULL 13/14] target/arm: Define neoverse-v1 Peter Maydell
2023-07-06 13:25 ` [PULL 14/14] target/arm: Avoid over-length shift in arm_cpu_sve_finalize() error case Peter Maydell
2023-07-06 17:19 ` [PULL v2 00/14] target-arm queue Richard Henderson

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