From: Daniel Henrique Barboza <danielhb413@gmail.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com,
peter.maydell@linaro.org, richard.henderson@linaro.org,
BALATON Zoltan <balaton@eik.bme.hu>,
Nicholas Piggin <npiggin@gmail.com>
Subject: [PULL 14/60] target/ppc: Move common check in exception handlers to a function
Date: Fri, 7 Jul 2023 08:30:22 -0300 [thread overview]
Message-ID: <20230707113108.7145-15-danielhb413@gmail.com> (raw)
In-Reply-To: <20230707113108.7145-1-danielhb413@gmail.com>
From: BALATON Zoltan <balaton@eik.bme.hu>
All powerpc exception handlers share some code when handling machine
check exceptions. Move this to a common function.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <9cfffaa35aa894086dd092af6b0b26f2d62ff3de.1686868895.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/excp_helper.c | 114 +++++++++------------------------------
1 file changed, 25 insertions(+), 89 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 3ddec06f65..d1d3d089a6 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -424,6 +424,25 @@ static void powerpc_set_excp_state(PowerPCCPU *cpu, target_ulong vector,
env->reserve_addr = -1;
}
+static void powerpc_mcheck_checkstop(CPUPPCState *env)
+{
+ CPUState *cs = env_cpu(env);
+
+ if (FIELD_EX64(env->msr, MSR, ME)) {
+ return;
+ }
+
+ /* Machine check exception is not enabled. Enter checkstop state. */
+ fprintf(stderr, "Machine check while not allowed. "
+ "Entering checkstop state\n");
+ if (qemu_log_separate()) {
+ qemu_log("Machine check while not allowed. "
+ "Entering checkstop state\n");
+ }
+ cs->halted = 1;
+ cpu_interrupt_exittb(cs);
+}
+
static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
{
CPUState *cs = CPU(cpu);
@@ -466,21 +485,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
srr1 = SPR_40x_SRR3;
break;
case POWERPC_EXCP_MCHECK: /* Machine check exception */
- if (!FIELD_EX64(env->msr, MSR, ME)) {
- /*
- * Machine check exception is not enabled. Enter
- * checkstop state.
- */
- fprintf(stderr, "Machine check while not allowed. "
- "Entering checkstop state\n");
- if (qemu_log_separate()) {
- qemu_log("Machine check while not allowed. "
- "Entering checkstop state\n");
- }
- cs->halted = 1;
- cpu_interrupt_exittb(cs);
- }
-
+ powerpc_mcheck_checkstop(env);
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
@@ -597,21 +602,7 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_CRITICAL: /* Critical input */
break;
case POWERPC_EXCP_MCHECK: /* Machine check exception */
- if (!FIELD_EX64(env->msr, MSR, ME)) {
- /*
- * Machine check exception is not enabled. Enter
- * checkstop state.
- */
- fprintf(stderr, "Machine check while not allowed. "
- "Entering checkstop state\n");
- if (qemu_log_separate()) {
- qemu_log("Machine check while not allowed. "
- "Entering checkstop state\n");
- }
- cs->halted = 1;
- cpu_interrupt_exittb(cs);
- }
-
+ powerpc_mcheck_checkstop(env);
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
@@ -770,21 +761,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
switch (excp) {
case POWERPC_EXCP_MCHECK: /* Machine check exception */
- if (!FIELD_EX64(env->msr, MSR, ME)) {
- /*
- * Machine check exception is not enabled. Enter
- * checkstop state.
- */
- fprintf(stderr, "Machine check while not allowed. "
- "Entering checkstop state\n");
- if (qemu_log_separate()) {
- qemu_log("Machine check while not allowed. "
- "Entering checkstop state\n");
- }
- cs->halted = 1;
- cpu_interrupt_exittb(cs);
- }
-
+ powerpc_mcheck_checkstop(env);
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
@@ -955,21 +932,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
switch (excp) {
case POWERPC_EXCP_MCHECK: /* Machine check exception */
- if (!FIELD_EX64(env->msr, MSR, ME)) {
- /*
- * Machine check exception is not enabled. Enter
- * checkstop state.
- */
- fprintf(stderr, "Machine check while not allowed. "
- "Entering checkstop state\n");
- if (qemu_log_separate()) {
- qemu_log("Machine check while not allowed. "
- "Entering checkstop state\n");
- }
- cs->halted = 1;
- cpu_interrupt_exittb(cs);
- }
-
+ powerpc_mcheck_checkstop(env);
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
@@ -1150,21 +1113,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
srr1 = SPR_BOOKE_CSRR1;
break;
case POWERPC_EXCP_MCHECK: /* Machine check exception */
- if (!FIELD_EX64(env->msr, MSR, ME)) {
- /*
- * Machine check exception is not enabled. Enter
- * checkstop state.
- */
- fprintf(stderr, "Machine check while not allowed. "
- "Entering checkstop state\n");
- if (qemu_log_separate()) {
- qemu_log("Machine check while not allowed. "
- "Entering checkstop state\n");
- }
- cs->halted = 1;
- cpu_interrupt_exittb(cs);
- }
-
+ powerpc_mcheck_checkstop(env);
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
@@ -1467,20 +1416,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
switch (excp) {
case POWERPC_EXCP_MCHECK: /* Machine check exception */
- if (!FIELD_EX64(env->msr, MSR, ME)) {
- /*
- * Machine check exception is not enabled. Enter
- * checkstop state.
- */
- fprintf(stderr, "Machine check while not allowed. "
- "Entering checkstop state\n");
- if (qemu_log_separate()) {
- qemu_log("Machine check while not allowed. "
- "Entering checkstop state\n");
- }
- cs->halted = 1;
- cpu_interrupt_exittb(cs);
- }
+ powerpc_mcheck_checkstop(env);
if (env->msr_mask & MSR_HVB) {
/*
* ISA specifies HV, but can be delivered to guest with HV
--
2.41.0
next prev parent reply other threads:[~2023-07-07 11:41 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-07 11:30 [PULL 00/60] ppc queue Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 01/60] pnv/psi: Allow access to PSI registers through xscom Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 02/60] target/ppc: Make HDECR underflow edge triggered Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 03/60] hw/ppc: Fix clock update drift Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 04/60] target/ppc: Only generate decodetree files when TCG is enabled Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 05/60] mv64361: Add dummy gigabit ethernet PHY access registers Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 06/60] target/ppc: Tidy POWER book4 SPR registration Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 07/60] target/ppc: Add TFMR SPR implementation with read and write helpers Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 08/60] sungem: Add WOL MMIO Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 09/60] target/ppc: Fix icount access for some hypervisor instructions Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 10/60] tests/avocado: record_replay test for ppc powernv machine Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 11/60] pnv/xive2: Allow indirect TIMA accesses of all sizes Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 12/60] target/ppc: Remove some superfluous parentheses Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 13/60] target/ppc: Remove unneeded parameter from powerpc_reset_wakeup() Daniel Henrique Barboza
2023-07-07 11:30 ` Daniel Henrique Barboza [this message]
2023-07-07 11:30 ` [PULL 15/60] target/ppc: Remove some more local CPUState variables only used once Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 16/60] target/ppd: Remove unused define Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 17/60] target/ppc: Get CPUState in one step Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 18/60] target: ppc: Use MSR_HVB bit to get the target endianness for memory dump Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 19/60] pnv/xive2: Fix TIMA offset for indirect access Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 20/60] pnv/xive: Add property on xive sources to define PQ state on reset Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 21/60] pnv/psi: Initialize the PSIHB interrupts to match hardware Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 22/60] ppc/pnv: quad xscom callbacks are P9 specific Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 23/60] ppc/pnv: Subclass quad xscom callbacks Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 24/60] ppc/pnv: Add P10 quad xscom model Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 25/60] ppc/pnv: Add P10 core " Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 26/60] ppc/pnv: Return zero for core thread state xscom Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 27/60] pnv/xive: Allow mmio operations of any size on the ESB CI pages Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 28/60] ppc/pegasos2: Add support for -initrd command line option Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 29/60] pnv/xive: Print CPU target in all TIMA traces Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 30/60] pnv/xive2: Always pass a presenter object when accessing the TIMA Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 31/60] target/ppc: Add LPAR-per-core vs per-thread mode flag Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 32/60] target/ppc: SMT support for the HID SPR Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 33/60] ppc/pnv: SMT support for powernv Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 34/60] tests/avocado: Add powernv machine test script Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 35/60] ppc440: Change ppc460ex_pcie_init() parameter type Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 36/60] ppc440: Add cpu link property to PCIe controller model Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 37/60] ppc440: Add a macro to shorten PCIe controller DCR registration Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 38/60] ppc440: Rename parent field of PPC460EXPCIEState to match code style Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 39/60] ppc440: Rename local variable in dcr_read_pcie() Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 40/60] ppc440: Stop using system io region for PCIe buses Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 41/60] ppc440: Add busnum property to PCIe controller model Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 42/60] ppc440: Remove ppc460ex_pcie_init legacy init function Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 43/60] ppc/sam460ex: Remove address_space_mem local variable Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 44/60] ppc440_pcix: Don't use iomem for regs Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 45/60] ppc440_pcix: Stop using system io region for PCI bus Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 46/60] ppc4xx_pci: Rename QOM type name define Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 47/60] ppc4xx_pci: Add define for ppc4xx-host-bridge type name Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 48/60] ppc440_pcix: Rename QOM type define abd move it to common header Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 49/60] ppc/pnv: Log all unimp warnings with similar message Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 50/60] ppc/pnv: Set P10 core xscom region size to match hardware Daniel Henrique Barboza
2023-07-07 11:30 ` [PULL 51/60] tests/qtest: Add xscom tests for powernv10 machine Daniel Henrique Barboza
2023-07-07 11:31 ` [PULL 52/60] target/ppc: Machine check on invalid real address access on POWER9/10 Daniel Henrique Barboza
2023-07-07 11:31 ` [PULL 53/60] target/ppc: Have 'kvm_ppc.h' include 'sysemu/kvm.h' Daniel Henrique Barboza
2023-07-07 11:31 ` [PULL 54/60] target/ppc: Reorder #ifdef'ry in kvm_ppc.h Daniel Henrique Barboza
2023-07-07 11:31 ` [PULL 55/60] target/ppc: Move CPU QOM definitions to cpu-qom.h Daniel Henrique Barboza
2023-07-07 11:31 ` [PULL 56/60] target/ppc: Define TYPE_HOST_POWERPC_CPU in cpu-qom.h Daniel Henrique Barboza
2023-07-07 11:31 ` [PULL 57/60] target/ppc: Restrict 'kvm_ppc.h' to sysemu in cpu_init.c Daniel Henrique Barboza
2023-07-07 11:31 ` [PULL 58/60] target/ppc: Remove pointless checks of CONFIG_USER_ONLY in 'kvm_ppc.h' Daniel Henrique Barboza
2023-07-07 11:31 ` [PULL 59/60] ppc/pnv: Add QME region for P10 Daniel Henrique Barboza
2023-07-07 11:31 ` [PULL 60/60] ppc: Enable 2nd DAWR support on p10 Daniel Henrique Barboza
2023-07-07 14:29 ` [PULL 00/60] ppc queue Daniel Henrique Barboza
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