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Tsirkin" To: Ani Sinha Cc: Akihiko Odaki , qemu-devel , qemu-block@nongnu.org, Igor Mammedov , Marcel Apfelbaum , Sriram Yagnaraman , Jason Wang , Keith Busch , Klaus Jensen Subject: Re: [PATCH v5 2/2] pcie: Specify 0 for ARI next function numbers Message-ID: <20230710075925-mutt-send-email-mst@kernel.org> References: <20230705022421.13115-1-akihiko.odaki@daynix.com> <20230705022421.13115-3-akihiko.odaki@daynix.com> <20230710051539-mutt-send-email-mst@kernel.org> <20230710054117-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Jul 10, 2023 at 03:44:04PM +0530, Ani Sinha wrote: > > > > On 10-Jul-2023, at 3:14 PM, Michael S. Tsirkin wrote: > > > > On Mon, Jul 10, 2023 at 02:49:55PM +0530, Ani Sinha wrote: > >> > >> > >>> On 10-Jul-2023, at 2:46 PM, Michael S. Tsirkin wrote: > >>> > >>> On Mon, Jul 10, 2023 at 01:21:50PM +0530, Ani Sinha wrote: > >>>> > >>>> > >>>>> On 05-Jul-2023, at 7:54 AM, Akihiko Odaki wrote: > >>>>> > >>>>> The current implementers of ARI are all SR-IOV devices. The ARI next > >>>>> function number field is undefined for VF according to PCI Express Base > >>>>> Specification Revision 5.0 Version 1.0 section 9.3.7.7. The PF should > >>>>> end the linked list formed with the field by specifying 0 according to > >>>>> section 7.8.7.2. > >>>> > >>>> Section 7.8.7.2 ARI Capability Register (Offset 04h), I see only this > >>>> > >>>> Next Function Number - This field indicates the Function Number of the next higher numbered Function in the Device, or 00h if there are no higher numbered Functions. Function 0 starts this linked list of Functions. > >>>> > >>>> I do not see anything specifically for PF. What am I missing? > >>> > >>> This is *only* for PFs. > >> > >> I think this covers both SRIOV and non SRIOV cases both. This is a > >> general case for all devices, PF or other non-SRIOV capable devices. > > > > "this" being what? > > “this” is the following line I quoted above: > > "Next Function Number - This field indicates the Function Number of the next higher numbered Function in the Device, or 00h if there are no higher numbered Functions. Function 0 starts this linked list of Functions.” > > I think it applies for all devices in general (except VFs). For all functions of devices with ARI support, yes. Does not apply to VFs. > > I'm talking about the pci spec text > > you quoted. > > > > check out the sriov spec: > > Next Function Number – VFs are located using First > > VF Offset (see Section 3.3.9) and VF Stride (see > > Section 3.3.10). > > > > > > > >>> There's separate text explaining that > >>> VFs use NumVFs VFOffset and VFStride. > >>> > >>> > >>>>> > >>>>> For migration, the field will keep having 1 as its value on the old > >>>>> virt models. > >>>>> > >>>>> Fixes: 2503461691 ("pcie: Add some SR/IOV API documentation in docs/pcie_sriov.txt") > >>>>> Fixes: 44c2c09488 ("hw/nvme: Add support for SR-IOV") > >>>>> Fixes: 3a977deebe ("Intrdocue igb device emulation") > >>>>> Signed-off-by: Akihiko Odaki > >>>>> --- > >>>>> include/hw/pci/pci.h | 2 ++ > >>>>> hw/core/machine.c | 1 + > >>>>> hw/pci/pci.c | 2 ++ > >>>>> hw/pci/pcie.c | 2 +- > >>>>> 4 files changed, 6 insertions(+), 1 deletion(-) > >>>>> > >>>>> diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h > >>>>> index e6d0574a29..9c5b5eb206 100644 > >>>>> --- a/include/hw/pci/pci.h > >>>>> +++ b/include/hw/pci/pci.h > >>>>> @@ -209,6 +209,8 @@ enum { > >>>>> QEMU_PCIE_CAP_CXL = (1 << QEMU_PCIE_CXL_BITNR), > >>>>> #define QEMU_PCIE_ERR_UNC_MASK_BITNR 11 > >>>>> QEMU_PCIE_ERR_UNC_MASK = (1 << QEMU_PCIE_ERR_UNC_MASK_BITNR), > >>>>> +#define QEMU_PCIE_ARI_NEXTFN_1_BITNR 12 > >>>>> + QEMU_PCIE_ARI_NEXTFN_1 = (1 << QEMU_PCIE_ARI_NEXTFN_1_BITNR), > >>>>> }; > >>>>> > >>>>> typedef struct PCIINTxRoute { > >>>>> diff --git a/hw/core/machine.c b/hw/core/machine.c > >>>>> index 46f8f9a2b0..f0d35c6401 100644 > >>>>> --- a/hw/core/machine.c > >>>>> +++ b/hw/core/machine.c > >>>>> @@ -41,6 +41,7 @@ > >>>>> > >>>>> GlobalProperty hw_compat_8_0[] = { > >>>>> { "migration", "multifd-flush-after-each-section", "on"}, > >>>>> + { TYPE_PCI_DEVICE, "x-pcie-ari-nextfn-1", "on" }, > >>>>> }; > >>>>> const size_t hw_compat_8_0_len = G_N_ELEMENTS(hw_compat_8_0); > >>>>> > >>>>> diff --git a/hw/pci/pci.c b/hw/pci/pci.c > >>>>> index e2eb4c3b4a..45a9bc0da8 100644 > >>>>> --- a/hw/pci/pci.c > >>>>> +++ b/hw/pci/pci.c > >>>>> @@ -82,6 +82,8 @@ static Property pci_props[] = { > >>>>> DEFINE_PROP_UINT32("acpi-index", PCIDevice, acpi_index, 0), > >>>>> DEFINE_PROP_BIT("x-pcie-err-unc-mask", PCIDevice, cap_present, > >>>>> QEMU_PCIE_ERR_UNC_MASK_BITNR, true), > >>>>> + DEFINE_PROP_BIT("x-pcie-ari-nextfn-1", PCIDevice, cap_present, > >>>>> + QEMU_PCIE_ARI_NEXTFN_1_BITNR, false), > >>>>> DEFINE_PROP_END_OF_LIST() > >>>>> }; > >>>>> > >>>>> diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c > >>>>> index 9a3f6430e8..cf09e03a10 100644 > >>>>> --- a/hw/pci/pcie.c > >>>>> +++ b/hw/pci/pcie.c > >>>>> @@ -1030,7 +1030,7 @@ void pcie_sync_bridge_lnk(PCIDevice *bridge_dev) > >>>>> /* ARI */ > >>>>> void pcie_ari_init(PCIDevice *dev, uint16_t offset) > >>>>> { > >>>>> - uint16_t nextfn = 1; > >>>>> + uint16_t nextfn = dev->cap_present & QEMU_PCIE_ARI_NEXTFN_1 ? 1 : 0; > >>>>> > >>>>> pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER, > >>>>> offset, PCI_ARI_SIZEOF); > >>>>> -- > >>>>> 2.41.0 > >>>>> > >>> > >