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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Siarhei Volkau" <lis8215@gmail.com>,
	"Huacai Chen" <chenhuacai@kernel.org>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Jiaxun Yang" <jiaxun.yang@flygoat.com>
Subject: [PULL 09/44] target/mips/mxu: Fix D16MAX D16MIN Q8MAX Q8MIN instructions
Date: Tue, 11 Jul 2023 00:25:36 +0200	[thread overview]
Message-ID: <20230710222611.50978-10-philmd@linaro.org> (raw)
In-Reply-To: <20230710222611.50978-1-philmd@linaro.org>

From: Siarhei Volkau <lis8215@gmail.com>

These instructions were designed that they overwrite source
register during partial storing of result.

Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-7-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/mips/tcg/mxu_translate.c | 30 ++++++++++++++++++------------
 1 file changed, 18 insertions(+), 12 deletions(-)

diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index 6d25562710..e63b4754be 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -1241,13 +1241,14 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
         /* ...and do half-word-wise max/min with one operand 0 */
         TCGv_i32 t0 = tcg_temp_new();
         TCGv_i32 t1 = tcg_constant_i32(0);
+        TCGv_i32 t2 = tcg_temp_new();
 
         /* the left half-word first */
         tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFFFF0000);
         if (opc == OPC_MXU_D16MAX) {
-            tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1);
+            tcg_gen_smax_i32(t2, t0, t1);
         } else {
-            tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1);
+            tcg_gen_smin_i32(t2, t0, t1);
         }
 
         /* the right half-word */
@@ -1263,7 +1264,7 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
         /* return resulting half-words to its original position */
         tcg_gen_shri_i32(t0, t0, 16);
         /* finally update the destination */
-        tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
+        tcg_gen_or_i32(mxu_gpr[XRa - 1], t2, t0);
     } else if (unlikely(XRb == XRc)) {
         /* both operands same -> just set destination to one of them */
         tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
@@ -1271,14 +1272,15 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
         /* the most general case */
         TCGv_i32 t0 = tcg_temp_new();
         TCGv_i32 t1 = tcg_temp_new();
+        TCGv_i32 t2 = tcg_temp_new();
 
         /* the left half-word first */
         tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFFFF0000);
         tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFFFF0000);
         if (opc == OPC_MXU_D16MAX) {
-            tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1);
+            tcg_gen_smax_i32(t2, t0, t1);
         } else {
-            tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1);
+            tcg_gen_smin_i32(t2, t0, t1);
         }
 
         /* the right half-word */
@@ -1296,7 +1298,7 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
         /* return resulting half-words to its original position */
         tcg_gen_shri_i32(t0, t0, 16);
         /* finally update the destination */
-        tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
+        tcg_gen_or_i32(mxu_gpr[XRa - 1], t2, t0);
     }
 }
 
@@ -1332,14 +1334,15 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
         /* ...and do byte-wise max/min with one operand 0 */
         TCGv_i32 t0 = tcg_temp_new();
         TCGv_i32 t1 = tcg_constant_i32(0);
+        TCGv_i32 t2 = tcg_temp_new();
         int32_t i;
 
         /* the leftmost byte (byte 3) first */
         tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFF000000);
         if (opc == OPC_MXU_Q8MAX) {
-            tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1);
+            tcg_gen_smax_i32(t2, t0, t1);
         } else {
-            tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1);
+            tcg_gen_smin_i32(t2, t0, t1);
         }
 
         /* bytes 2, 1, 0 */
@@ -1357,8 +1360,9 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
             /* return resulting byte to its original position */
             tcg_gen_shri_i32(t0, t0, 8 * (3 - i));
             /* finally update the destination */
-            tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
+            tcg_gen_or_i32(t2, t2, t0);
         }
+        gen_store_mxu_gpr(t2, XRa);
     } else if (unlikely(XRb == XRc)) {
         /* both operands same -> just set destination to one of them */
         tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
@@ -1366,15 +1370,16 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
         /* the most general case */
         TCGv_i32 t0 = tcg_temp_new();
         TCGv_i32 t1 = tcg_temp_new();
+        TCGv_i32 t2 = tcg_temp_new();
         int32_t i;
 
         /* the leftmost bytes (bytes 3) first */
         tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFF000000);
         tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFF000000);
         if (opc == OPC_MXU_Q8MAX) {
-            tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1);
+            tcg_gen_smax_i32(t2, t0, t1);
         } else {
-            tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1);
+            tcg_gen_smin_i32(t2, t0, t1);
         }
 
         /* bytes 2, 1, 0 */
@@ -1394,8 +1399,9 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
             /* return resulting byte to its original position */
             tcg_gen_shri_i32(t0, t0, 8 * (3 - i));
             /* finally update the destination */
-            tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
+            tcg_gen_or_i32(t2, t2, t0);
         }
+        gen_store_mxu_gpr(t2, XRa);
     }
 }
 
-- 
2.38.1



  parent reply	other threads:[~2023-07-10 22:29 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-10 22:25 [PULL 00/44] MIPS patches for 2023-07-10 Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 01/44] target/mips: Rework cp0_timer with clock API Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 02/44] target/mips: Implement Loongson CSR instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 03/44] hw/mips/loongson3_virt: Relax CPU restrictions for TCG Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 04/44] target/mips: Add emulation of MXU instructions for 32-bit load/store Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 05/44] target/mips: Add support of two XBurst CPUs Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 06/44] target/mips/mxu: Add LXW LXB LXH LXBU LXHU instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 07/44] target/mips/mxu: Add S32MADD/MADDU/MSUB/MSUBU instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 08/44] target/mips/mxu: Add Q8SLT Q8SLTU instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` Philippe Mathieu-Daudé [this message]
2023-07-10 22:25 ` [PULL 10/44] target/mips/mxu: Add S32SLT D16SLT D16AVG[R] Q8AVG[R] insns Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 11/44] target/mips/mxu: Add Q8ADD instruction Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 12/44] target/mips/mxu: Add S32CPS D16CPS Q8ABD Q16SAT insns Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 13/44] target/mips/mxu: Add D16MULF D16MULE instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 14/44] target/mips/mxu: Add D16MACF D16MACE instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 15/44] target/mips/mxu: Add D16MADL instruction Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 16/44] target/mips/mxu: Add S16MAD instruction Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 17/44] target/mips/mxu: Add Q16ADD instruction Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 18/44] target/mips/mxu: Add D32ADD instruction Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 19/44] target/mips/mxu: Add D32ACC D32ACCM D32ASUM instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 20/44] target/mips/mxu: Add D32ADDC instruction Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 21/44] target/mips/mxu: Add Q16ACC Q16ACCM D16ASUM instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 22/44] target/mips/mxu: Add Q8ADDE Q8ACCE D8SUM D8SUMC instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 23/44] target/mips/mxu: Add S8STD S8LDI S8SDI instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 24/44] target/mips/mxu: Add S16LDD S16STD S16LDI S16SDI instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 25/44] target/mips/mxu: Add S32MUL S32MULU S32EXTR S32EXTRV insns Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 26/44] target/mips/mxu: Add S32ALN S32LUI insns Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 27/44] target/mips/mxu: Add D32SARL D32SARW instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 28/44] target/mips/mxu: Add D32SLL D32SLR D32SAR instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 29/44] target/mips/mxu: Add Q16SLL Q16SLR Q16SAR instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 30/44] target/mips/mxu: Add D32/Q16- SLLV/SLRV/SARV instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 31/44] target/mips/mxu: Add S32/D16/Q8- MOVZ/MOVN instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 32/44] target/mips/mxu: Add Q8MAC Q8MACSU instructions Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 33/44] target/mips/mxu: Add Q16SCOP instruction Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 34/44] target/mips/mxu: Add Q8MADL instruction Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 35/44] target/mips/mxu: Add S32SFL instruction Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 36/44] target/mips/mxu: Add Q8SAD instruction Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 37/44] target/mips: enable GINVx support for I6400 and I6500 Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 38/44] hw/ide/pci: Expose legacy interrupts as named GPIOs Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 39/44] hw/ide/via: Wire up IDE legacy interrupts in host device Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 40/44] hw/isa/vt82c686: Remove via_isa_set_irq() Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 41/44] hw/ide: Extract IDEBus assignment into bmdma_init() Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 42/44] hw/ide: Extract bmdma_status_writeb() Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 43/44] hw/ide/pci: Replace some magic numbers by constants Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 44/44] hw/ide/piix: Move registration of VMStateDescription to DeviceClass Philippe Mathieu-Daudé
2023-07-11  8:32 ` [PULL 00/44] MIPS patches for 2023-07-10 Richard Henderson

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