From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Siarhei Volkau" <lis8215@gmail.com>,
"Huacai Chen" <chenhuacai@kernel.org>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>
Subject: [PULL 10/44] target/mips/mxu: Add S32SLT D16SLT D16AVG[R] Q8AVG[R] insns
Date: Tue, 11 Jul 2023 00:25:37 +0200 [thread overview]
Message-ID: <20230710222611.50978-11-philmd@linaro.org> (raw)
In-Reply-To: <20230710222611.50978-1-philmd@linaro.org>
From: Siarhei Volkau <lis8215@gmail.com>
These instructions are part of pool1, see the grand tree above
in the file. Q8ADD is part of pool1 too but belong to another
category of instructions, thus will be made in later patches.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-8-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/mxu_translate.c | 244 +++++++++++++++++++++++++++++++-
1 file changed, 243 insertions(+), 1 deletion(-)
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index e63b4754be..f170195feb 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -358,6 +358,7 @@ enum {
OPC_MXU__POOL00 = 0x03,
OPC_MXU_S32MSUB = 0x04,
OPC_MXU_S32MSUBU = 0x05,
+ OPC_MXU__POOL01 = 0x06,
OPC_MXU_D16MUL = 0x08,
OPC_MXU_D16MAC = 0x0A,
OPC_MXU__POOL04 = 0x10,
@@ -391,6 +392,18 @@ enum {
OPC_MXU_Q8SLTU = 0x07,
};
+/*
+ * MXU pool 01
+ */
+enum {
+ OPC_MXU_S32SLT = 0x00,
+ OPC_MXU_D16SLT = 0x01,
+ OPC_MXU_D16AVG = 0x02,
+ OPC_MXU_D16AVGR = 0x03,
+ OPC_MXU_Q8AVG = 0x04,
+ OPC_MXU_Q8AVGR = 0x05,
+};
+
/*
* MXU pool 04 05 06 07 08 09 10 11
*/
@@ -1152,11 +1165,15 @@ static void gen_mxu_S32XOR(DisasContext *ctx)
/*
- * MXU instruction category max/min
+ * MXU instruction category max/min/avg
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*
* S32MAX D16MAX Q8MAX
* S32MIN D16MIN Q8MIN
+ * S32SLT D16SLT Q8SLT
+ * Q8SLTU
+ * D16AVG Q8AVG
+ * D16AVGR Q8AVGR
*/
/*
@@ -1462,6 +1479,199 @@ static void gen_mxu_q8slt(DisasContext *ctx, bool sltu)
}
}
+/*
+ * S32SLT
+ * Update XRa with the signed "set less than" comparison of XRb and XRc.
+ * a.k.a. XRa = XRb < XRc ? 1 : 0;
+ */
+static void gen_mxu_S32SLT(DisasContext *ctx)
+{
+ uint32_t pad, XRc, XRb, XRa;
+
+ pad = extract32(ctx->opcode, 21, 5);
+ XRc = extract32(ctx->opcode, 14, 4);
+ XRb = extract32(ctx->opcode, 10, 4);
+ XRa = extract32(ctx->opcode, 6, 4);
+
+ if (unlikely(pad != 0)) {
+ /* opcode padding incorrect -> do nothing */
+ } else if (unlikely(XRa == 0)) {
+ /* destination is zero register -> do nothing */
+ } else if (unlikely((XRb == 0) && (XRc == 0))) {
+ /* both operands zero registers -> just set destination to zero */
+ tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
+ } else if (unlikely(XRb == XRc)) {
+ /* both operands same registers -> just set destination to zero */
+ tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
+ } else {
+ /* the most general case */
+ tcg_gen_setcond_tl(TCG_COND_LT, mxu_gpr[XRa - 1],
+ mxu_gpr[XRb - 1], mxu_gpr[XRc - 1]);
+ }
+}
+
+/*
+ * D16SLT
+ * Update XRa with the signed "set less than" comparison of XRb and XRc
+ * on per-word basis.
+ * a.k.a. XRa[0..1] = XRb[0..1] < XRc[0..1] ? 1 : 0;
+ */
+static void gen_mxu_D16SLT(DisasContext *ctx)
+{
+ uint32_t pad, XRc, XRb, XRa;
+
+ pad = extract32(ctx->opcode, 21, 5);
+ XRc = extract32(ctx->opcode, 14, 4);
+ XRb = extract32(ctx->opcode, 10, 4);
+ XRa = extract32(ctx->opcode, 6, 4);
+
+ if (unlikely(pad != 0)) {
+ /* opcode padding incorrect -> do nothing */
+ } else if (unlikely(XRa == 0)) {
+ /* destination is zero register -> do nothing */
+ } else if (unlikely((XRb == 0) && (XRc == 0))) {
+ /* both operands zero registers -> just set destination to zero */
+ tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
+ } else if (unlikely(XRb == XRc)) {
+ /* both operands same registers -> just set destination to zero */
+ tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
+ } else {
+ /* the most general case */
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+ TCGv t3 = tcg_temp_new();
+ TCGv t4 = tcg_temp_new();
+
+ gen_load_mxu_gpr(t3, XRb);
+ gen_load_mxu_gpr(t4, XRc);
+ tcg_gen_sextract_tl(t0, t3, 16, 16);
+ tcg_gen_sextract_tl(t1, t4, 16, 16);
+ tcg_gen_setcond_tl(TCG_COND_LT, t0, t0, t1);
+ tcg_gen_shli_tl(t2, t0, 16);
+ tcg_gen_sextract_tl(t0, t3, 0, 16);
+ tcg_gen_sextract_tl(t1, t4, 0, 16);
+ tcg_gen_setcond_tl(TCG_COND_LT, t0, t0, t1);
+ tcg_gen_or_tl(mxu_gpr[XRa - 1], t2, t0);
+ }
+}
+
+/*
+ * D16AVG
+ * Update XRa with the signed average of XRb and XRc
+ * on per-word basis, rounding down.
+ * a.k.a. XRa[0..1] = (XRb[0..1] + XRc[0..1]) >> 1;
+ *
+ * D16AVGR
+ * Update XRa with the signed average of XRb and XRc
+ * on per-word basis, math rounding 4/5.
+ * a.k.a. XRa[0..1] = (XRb[0..1] + XRc[0..1] + 1) >> 1;
+ */
+static void gen_mxu_d16avg(DisasContext *ctx, bool round45)
+{
+ uint32_t pad, XRc, XRb, XRa;
+
+ pad = extract32(ctx->opcode, 21, 5);
+ XRc = extract32(ctx->opcode, 14, 4);
+ XRb = extract32(ctx->opcode, 10, 4);
+ XRa = extract32(ctx->opcode, 6, 4);
+
+ if (unlikely(pad != 0)) {
+ /* opcode padding incorrect -> do nothing */
+ } else if (unlikely(XRa == 0)) {
+ /* destination is zero register -> do nothing */
+ } else if (unlikely((XRb == 0) && (XRc == 0))) {
+ /* both operands zero registers -> just set destination to zero */
+ tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
+ } else if (unlikely(XRb == XRc)) {
+ /* both operands same registers -> just set destination to same */
+ tcg_gen_mov_tl(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
+ } else {
+ /* the most general case */
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+ TCGv t3 = tcg_temp_new();
+ TCGv t4 = tcg_temp_new();
+
+ gen_load_mxu_gpr(t3, XRb);
+ gen_load_mxu_gpr(t4, XRc);
+ tcg_gen_sextract_tl(t0, t3, 16, 16);
+ tcg_gen_sextract_tl(t1, t4, 16, 16);
+ tcg_gen_add_tl(t0, t0, t1);
+ if (round45) {
+ tcg_gen_addi_tl(t0, t0, 1);
+ }
+ tcg_gen_shli_tl(t2, t0, 15);
+ tcg_gen_andi_tl(t2, t2, 0xffff0000);
+ tcg_gen_sextract_tl(t0, t3, 0, 16);
+ tcg_gen_sextract_tl(t1, t4, 0, 16);
+ tcg_gen_add_tl(t0, t0, t1);
+ if (round45) {
+ tcg_gen_addi_tl(t0, t0, 1);
+ }
+ tcg_gen_shri_tl(t0, t0, 1);
+ tcg_gen_deposit_tl(t2, t2, t0, 0, 16);
+ gen_store_mxu_gpr(t2, XRa);
+ }
+}
+
+/*
+ * Q8AVG
+ * Update XRa with the signed average of XRb and XRc
+ * on per-byte basis, rounding down.
+ * a.k.a. XRa[0..3] = (XRb[0..3] + XRc[0..3]) >> 1;
+ *
+ * Q8AVGR
+ * Update XRa with the signed average of XRb and XRc
+ * on per-word basis, math rounding 4/5.
+ * a.k.a. XRa[0..3] = (XRb[0..3] + XRc[0..3] + 1) >> 1;
+ */
+static void gen_mxu_q8avg(DisasContext *ctx, bool round45)
+{
+ uint32_t pad, XRc, XRb, XRa;
+
+ pad = extract32(ctx->opcode, 21, 5);
+ XRc = extract32(ctx->opcode, 14, 4);
+ XRb = extract32(ctx->opcode, 10, 4);
+ XRa = extract32(ctx->opcode, 6, 4);
+
+ if (unlikely(pad != 0)) {
+ /* opcode padding incorrect -> do nothing */
+ } else if (unlikely(XRa == 0)) {
+ /* destination is zero register -> do nothing */
+ } else if (unlikely((XRb == 0) && (XRc == 0))) {
+ /* both operands zero registers -> just set destination to zero */
+ tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
+ } else if (unlikely(XRb == XRc)) {
+ /* both operands same registers -> just set destination to same */
+ tcg_gen_mov_tl(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
+ } else {
+ /* the most general case */
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+ TCGv t3 = tcg_temp_new();
+ TCGv t4 = tcg_temp_new();
+
+ gen_load_mxu_gpr(t3, XRb);
+ gen_load_mxu_gpr(t4, XRc);
+ tcg_gen_movi_tl(t2, 0);
+
+ for (int i = 0; i < 4; i++) {
+ tcg_gen_extract_tl(t0, t3, 8 * i, 8);
+ tcg_gen_extract_tl(t1, t4, 8 * i, 8);
+ tcg_gen_add_tl(t0, t0, t1);
+ if (round45) {
+ tcg_gen_addi_tl(t0, t0, 1);
+ }
+ tcg_gen_shri_tl(t0, t0, 1);
+ tcg_gen_deposit_tl(t2, t2, t0, 8 * i, 8);
+ }
+ gen_store_mxu_gpr(t2, XRa);
+ }
+}
+
/*
* MXU instruction category: align
@@ -1769,6 +1979,35 @@ static bool decode_opc_mxu_s32madd_sub(DisasContext *ctx)
return true;
}
+static void decode_opc_mxu__pool01(DisasContext *ctx)
+{
+ uint32_t opcode = extract32(ctx->opcode, 18, 3);
+
+ switch (opcode) {
+ case OPC_MXU_S32SLT:
+ gen_mxu_S32SLT(ctx);
+ break;
+ case OPC_MXU_D16SLT:
+ gen_mxu_D16SLT(ctx);
+ break;
+ case OPC_MXU_D16AVG:
+ gen_mxu_d16avg(ctx, false);
+ break;
+ case OPC_MXU_D16AVGR:
+ gen_mxu_d16avg(ctx, true);
+ break;
+ case OPC_MXU_Q8AVG:
+ gen_mxu_q8avg(ctx, false);
+ break;
+ case OPC_MXU_Q8AVGR:
+ gen_mxu_q8avg(ctx, true);
+ break;
+ default:
+ MIPS_INVAL("decode_opc_mxu");
+ gen_reserved_instruction(ctx);
+ break;
+ }
+}
static void decode_opc_mxu__pool04(DisasContext *ctx)
{
uint32_t reversed = extract32(ctx->opcode, 20, 1);
@@ -2015,6 +2254,9 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn)
case OPC_MXU_D16MAC:
gen_mxu_d16mac(ctx);
break;
+ case OPC_MXU__POOL01:
+ decode_opc_mxu__pool01(ctx);
+ break;
case OPC_MXU__POOL04:
decode_opc_mxu__pool04(ctx);
break;
--
2.38.1
next prev parent reply other threads:[~2023-07-10 22:31 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-10 22:25 [PULL 00/44] MIPS patches for 2023-07-10 Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 01/44] target/mips: Rework cp0_timer with clock API Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 02/44] target/mips: Implement Loongson CSR instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 03/44] hw/mips/loongson3_virt: Relax CPU restrictions for TCG Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 04/44] target/mips: Add emulation of MXU instructions for 32-bit load/store Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 05/44] target/mips: Add support of two XBurst CPUs Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 06/44] target/mips/mxu: Add LXW LXB LXH LXBU LXHU instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 07/44] target/mips/mxu: Add S32MADD/MADDU/MSUB/MSUBU instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 08/44] target/mips/mxu: Add Q8SLT Q8SLTU instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 09/44] target/mips/mxu: Fix D16MAX D16MIN Q8MAX Q8MIN instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` Philippe Mathieu-Daudé [this message]
2023-07-10 22:25 ` [PULL 11/44] target/mips/mxu: Add Q8ADD instruction Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 12/44] target/mips/mxu: Add S32CPS D16CPS Q8ABD Q16SAT insns Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 13/44] target/mips/mxu: Add D16MULF D16MULE instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 14/44] target/mips/mxu: Add D16MACF D16MACE instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 15/44] target/mips/mxu: Add D16MADL instruction Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 16/44] target/mips/mxu: Add S16MAD instruction Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 17/44] target/mips/mxu: Add Q16ADD instruction Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 18/44] target/mips/mxu: Add D32ADD instruction Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 19/44] target/mips/mxu: Add D32ACC D32ACCM D32ASUM instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 20/44] target/mips/mxu: Add D32ADDC instruction Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 21/44] target/mips/mxu: Add Q16ACC Q16ACCM D16ASUM instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 22/44] target/mips/mxu: Add Q8ADDE Q8ACCE D8SUM D8SUMC instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 23/44] target/mips/mxu: Add S8STD S8LDI S8SDI instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 24/44] target/mips/mxu: Add S16LDD S16STD S16LDI S16SDI instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 25/44] target/mips/mxu: Add S32MUL S32MULU S32EXTR S32EXTRV insns Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 26/44] target/mips/mxu: Add S32ALN S32LUI insns Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 27/44] target/mips/mxu: Add D32SARL D32SARW instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 28/44] target/mips/mxu: Add D32SLL D32SLR D32SAR instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 29/44] target/mips/mxu: Add Q16SLL Q16SLR Q16SAR instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 30/44] target/mips/mxu: Add D32/Q16- SLLV/SLRV/SARV instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 31/44] target/mips/mxu: Add S32/D16/Q8- MOVZ/MOVN instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 32/44] target/mips/mxu: Add Q8MAC Q8MACSU instructions Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 33/44] target/mips/mxu: Add Q16SCOP instruction Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 34/44] target/mips/mxu: Add Q8MADL instruction Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 35/44] target/mips/mxu: Add S32SFL instruction Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 36/44] target/mips/mxu: Add Q8SAD instruction Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 37/44] target/mips: enable GINVx support for I6400 and I6500 Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 38/44] hw/ide/pci: Expose legacy interrupts as named GPIOs Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 39/44] hw/ide/via: Wire up IDE legacy interrupts in host device Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 40/44] hw/isa/vt82c686: Remove via_isa_set_irq() Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 41/44] hw/ide: Extract IDEBus assignment into bmdma_init() Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 42/44] hw/ide: Extract bmdma_status_writeb() Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 43/44] hw/ide/pci: Replace some magic numbers by constants Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 44/44] hw/ide/piix: Move registration of VMStateDescription to DeviceClass Philippe Mathieu-Daudé
2023-07-11 8:32 ` [PULL 00/44] MIPS patches for 2023-07-10 Richard Henderson
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