From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Siarhei Volkau" <lis8215@gmail.com>,
"Huacai Chen" <chenhuacai@kernel.org>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Bernhard Beschow" <shentey@gmail.com>,
"BALATON Zoltan" <balaton@eik.bme.hu>,
"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>
Subject: [PULL 41/44] hw/ide: Extract IDEBus assignment into bmdma_init()
Date: Tue, 11 Jul 2023 00:26:08 +0200 [thread overview]
Message-ID: <20230710222611.50978-42-philmd@linaro.org> (raw)
In-Reply-To: <20230710222611.50978-1-philmd@linaro.org>
From: Bernhard Beschow <shentey@gmail.com>
Every invocation of bmdma_init() is followed by `d->bmdma[i].bus = &d->bus[i]`.
Resolve this redundancy by extracting it into bmdma_init().
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20230531211043.41724-5-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/ide/cmd646.c | 1 -
hw/ide/pci.c | 1 +
hw/ide/piix.c | 1 -
hw/ide/sii3112.c | 1 -
hw/ide/via.c | 1 -
5 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
index a68357c1c5..a094a6e12a 100644
--- a/hw/ide/cmd646.c
+++ b/hw/ide/cmd646.c
@@ -297,7 +297,6 @@ static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
ide_bus_init_output_irq(&d->bus[i], qdev_get_gpio_in(ds, i));
bmdma_init(&d->bus[i], &d->bmdma[i], d);
- d->bmdma[i].bus = &d->bus[i];
ide_bus_register_restart_cb(&d->bus[i]);
}
}
diff --git a/hw/ide/pci.c b/hw/ide/pci.c
index 9a5a7089d4..4cf1e9c679 100644
--- a/hw/ide/pci.c
+++ b/hw/ide/pci.c
@@ -519,6 +519,7 @@ void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d)
bus->dma = &bm->dma;
bm->irq = bus->irq;
bus->irq = qemu_allocate_irq(bmdma_irq, bm, 0);
+ bm->bus = bus;
bm->pci_dev = d;
}
diff --git a/hw/ide/piix.c b/hw/ide/piix.c
index 41d60921e3..a32f7ccece 100644
--- a/hw/ide/piix.c
+++ b/hw/ide/piix.c
@@ -144,7 +144,6 @@ static bool pci_piix_init_bus(PCIIDEState *d, unsigned i, Error **errp)
ide_bus_init_output_irq(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
bmdma_init(&d->bus[i], &d->bmdma[i], d);
- d->bmdma[i].bus = &d->bus[i];
ide_bus_register_restart_cb(&d->bus[i]);
return true;
diff --git a/hw/ide/sii3112.c b/hw/ide/sii3112.c
index f9becdff8e..5dd3d03c29 100644
--- a/hw/ide/sii3112.c
+++ b/hw/ide/sii3112.c
@@ -287,7 +287,6 @@ static void sii3112_pci_realize(PCIDevice *dev, Error **errp)
ide_bus_init_output_irq(&s->bus[i], qdev_get_gpio_in(ds, i));
bmdma_init(&s->bus[i], &s->bmdma[i], s);
- s->bmdma[i].bus = &s->bus[i];
ide_bus_register_restart_cb(&s->bus[i]);
}
}
diff --git a/hw/ide/via.c b/hw/ide/via.c
index 0caae52276..91253fa4ef 100644
--- a/hw/ide/via.c
+++ b/hw/ide/via.c
@@ -196,7 +196,6 @@ static void via_ide_realize(PCIDevice *dev, Error **errp)
ide_bus_init_output_irq(&d->bus[i], qdev_get_gpio_in(ds, i));
bmdma_init(&d->bus[i], &d->bmdma[i], d);
- d->bmdma[i].bus = &d->bus[i];
ide_bus_register_restart_cb(&d->bus[i]);
}
}
--
2.38.1
next prev parent reply other threads:[~2023-07-10 22:33 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-10 22:25 [PULL 00/44] MIPS patches for 2023-07-10 Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 01/44] target/mips: Rework cp0_timer with clock API Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 02/44] target/mips: Implement Loongson CSR instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 03/44] hw/mips/loongson3_virt: Relax CPU restrictions for TCG Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 04/44] target/mips: Add emulation of MXU instructions for 32-bit load/store Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 05/44] target/mips: Add support of two XBurst CPUs Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 06/44] target/mips/mxu: Add LXW LXB LXH LXBU LXHU instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 07/44] target/mips/mxu: Add S32MADD/MADDU/MSUB/MSUBU instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 08/44] target/mips/mxu: Add Q8SLT Q8SLTU instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 09/44] target/mips/mxu: Fix D16MAX D16MIN Q8MAX Q8MIN instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 10/44] target/mips/mxu: Add S32SLT D16SLT D16AVG[R] Q8AVG[R] insns Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 11/44] target/mips/mxu: Add Q8ADD instruction Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 12/44] target/mips/mxu: Add S32CPS D16CPS Q8ABD Q16SAT insns Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 13/44] target/mips/mxu: Add D16MULF D16MULE instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 14/44] target/mips/mxu: Add D16MACF D16MACE instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 15/44] target/mips/mxu: Add D16MADL instruction Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 16/44] target/mips/mxu: Add S16MAD instruction Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 17/44] target/mips/mxu: Add Q16ADD instruction Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 18/44] target/mips/mxu: Add D32ADD instruction Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 19/44] target/mips/mxu: Add D32ACC D32ACCM D32ASUM instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 20/44] target/mips/mxu: Add D32ADDC instruction Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 21/44] target/mips/mxu: Add Q16ACC Q16ACCM D16ASUM instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 22/44] target/mips/mxu: Add Q8ADDE Q8ACCE D8SUM D8SUMC instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 23/44] target/mips/mxu: Add S8STD S8LDI S8SDI instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 24/44] target/mips/mxu: Add S16LDD S16STD S16LDI S16SDI instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 25/44] target/mips/mxu: Add S32MUL S32MULU S32EXTR S32EXTRV insns Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 26/44] target/mips/mxu: Add S32ALN S32LUI insns Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 27/44] target/mips/mxu: Add D32SARL D32SARW instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 28/44] target/mips/mxu: Add D32SLL D32SLR D32SAR instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 29/44] target/mips/mxu: Add Q16SLL Q16SLR Q16SAR instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 30/44] target/mips/mxu: Add D32/Q16- SLLV/SLRV/SARV instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 31/44] target/mips/mxu: Add S32/D16/Q8- MOVZ/MOVN instructions Philippe Mathieu-Daudé
2023-07-10 22:25 ` [PULL 32/44] target/mips/mxu: Add Q8MAC Q8MACSU instructions Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 33/44] target/mips/mxu: Add Q16SCOP instruction Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 34/44] target/mips/mxu: Add Q8MADL instruction Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 35/44] target/mips/mxu: Add S32SFL instruction Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 36/44] target/mips/mxu: Add Q8SAD instruction Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 37/44] target/mips: enable GINVx support for I6400 and I6500 Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 38/44] hw/ide/pci: Expose legacy interrupts as named GPIOs Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 39/44] hw/ide/via: Wire up IDE legacy interrupts in host device Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 40/44] hw/isa/vt82c686: Remove via_isa_set_irq() Philippe Mathieu-Daudé
2023-07-10 22:26 ` Philippe Mathieu-Daudé [this message]
2023-07-10 22:26 ` [PULL 42/44] hw/ide: Extract bmdma_status_writeb() Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 43/44] hw/ide/pci: Replace some magic numbers by constants Philippe Mathieu-Daudé
2023-07-10 22:26 ` [PULL 44/44] hw/ide/piix: Move registration of VMStateDescription to DeviceClass Philippe Mathieu-Daudé
2023-07-11 8:32 ` [PULL 00/44] MIPS patches for 2023-07-10 Richard Henderson
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