From: Max Chou <max.chou@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: dbarboza@ventanamicro.com, alistair23@gmail.com,
"Max Chou" <max.chou@sifive.com>,
"Frank Chang" <frank.chang@sifive.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Daniel P. Berrangé" <berrange@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
qemu-arm@nongnu.org
Subject: [PATCH v8 13/15] crypto: Create sm4_subword
Date: Wed, 12 Jul 2023 00:59:12 +0800 [thread overview]
Message-ID: <20230711165917.2629866-14-max.chou@sifive.com> (raw)
In-Reply-To: <20230711165917.2629866-1-max.chou@sifive.com>
Allows sharing of sm4_subword between different targets.
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
include/crypto/sm4.h | 8 ++++++++
target/arm/tcg/crypto_helper.c | 10 ++--------
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h
index 9bd3ebc62e8..de8245d8a71 100644
--- a/include/crypto/sm4.h
+++ b/include/crypto/sm4.h
@@ -3,4 +3,12 @@
extern const uint8_t sm4_sbox[256];
+static inline uint32_t sm4_subword(uint32_t word)
+{
+ return sm4_sbox[word & 0xff] |
+ sm4_sbox[(word >> 8) & 0xff] << 8 |
+ sm4_sbox[(word >> 16) & 0xff] << 16 |
+ sm4_sbox[(word >> 24) & 0xff] << 24;
+}
+
#endif
diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c
index fdd70abbfd6..7cadd61e124 100644
--- a/target/arm/tcg/crypto_helper.c
+++ b/target/arm/tcg/crypto_helper.c
@@ -614,10 +614,7 @@ static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm)
CR_ST_WORD(d, (i + 3) % 4) ^
CR_ST_WORD(n, i);
- t = sm4_sbox[t & 0xff] |
- sm4_sbox[(t >> 8) & 0xff] << 8 |
- sm4_sbox[(t >> 16) & 0xff] << 16 |
- sm4_sbox[(t >> 24) & 0xff] << 24;
+ t = sm4_subword(t);
CR_ST_WORD(d, i) ^= t ^ rol32(t, 2) ^ rol32(t, 10) ^ rol32(t, 18) ^
rol32(t, 24);
@@ -651,10 +648,7 @@ static void do_crypto_sm4ekey(uint64_t *rd, uint64_t *rn, uint64_t *rm)
CR_ST_WORD(d, (i + 3) % 4) ^
CR_ST_WORD(m, i);
- t = sm4_sbox[t & 0xff] |
- sm4_sbox[(t >> 8) & 0xff] << 8 |
- sm4_sbox[(t >> 16) & 0xff] << 16 |
- sm4_sbox[(t >> 24) & 0xff] << 24;
+ t = sm4_subword(t);
CR_ST_WORD(d, i) ^= t ^ rol32(t, 13) ^ rol32(t, 23);
}
--
2.34.1
next prev parent reply other threads:[~2023-07-11 17:03 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-11 16:58 [PATCH v8 00/15] Add RISC-V vector cryptographic instruction set support Max Chou
2023-07-11 16:59 ` [PATCH v8 01/15] target/riscv: Refactor some of the generic vector functionality Max Chou
2023-07-19 0:54 ` Alistair Francis
2023-07-11 16:59 ` [PATCH v8 02/15] target/riscv: Refactor vector-vector translation macro Max Chou
2023-07-11 16:59 ` [PATCH v8 03/15] target/riscv: Remove redundant "cpu_vl == 0" checks Max Chou
2023-08-02 14:22 ` Alistair Francis
2023-07-11 16:59 ` [PATCH v8 04/15] target/riscv: Add Zvbc ISA extension support Max Chou
2023-08-02 14:29 ` Alistair Francis
2023-07-11 16:59 ` [PATCH v8 05/15] target/riscv: Move vector translation checks Max Chou
2023-07-11 16:59 ` [PATCH v8 06/15] target/riscv: Refactor translation of vector-widening instruction Max Chou
2023-07-11 16:59 ` [PATCH v8 07/15] target/riscv: Refactor some of the generic vector functionality Max Chou
2023-07-11 16:59 ` [PATCH v8 08/15] target/riscv: Add Zvbb ISA extension support Max Chou
2023-08-02 14:38 ` Alistair Francis
2023-07-11 16:59 ` [PATCH v8 09/15] target/riscv: Add Zvkned " Max Chou
2023-07-11 16:59 ` [PATCH v8 10/15] target/riscv: Add Zvknh " Max Chou
2023-07-11 16:59 ` [PATCH v8 11/15] target/riscv: Add Zvksh " Max Chou
2023-07-11 16:59 ` [PATCH v8 12/15] target/riscv: Add Zvkg " Max Chou
2023-07-11 16:59 ` Max Chou [this message]
2023-07-11 16:59 ` [PATCH v8 14/15] crypto: Add SM4 constant parameter CK Max Chou
2023-08-02 14:45 ` Alistair Francis
2023-07-11 16:59 ` [PATCH v8 15/15] target/riscv: Add Zvksed ISA extension support Max Chou
2023-08-02 14:54 ` [PATCH v8 00/15] Add RISC-V vector cryptographic instruction set support Alistair Francis
2023-08-03 4:16 ` Max Chou
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