qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Conor Dooley <conor@kernel.org>
To: Anup Patel <anup@brainfault.org>
Cc: Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
	alistair.francis@wdc.com, bmeng@tinylab.org,
	liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com,
	palmer@rivosinc.com, opensbi@lists.infradead.org
Subject: Re: Boot failure after QEMU's upgrade to OpenSBI v1.3 (was Re: [PATCH for-8.2 6/7] target/riscv: add 'max' CPU type)
Date: Fri, 14 Jul 2023 13:28:50 +0100	[thread overview]
Message-ID: <20230714-hash-handwrite-339817b93ba1@spud> (raw)
In-Reply-To: <20230714-reoccur-confined-4b37494b1201@spud>

[-- Attachment #1: Type: text/plain, Size: 2991 bytes --]

On Fri, Jul 14, 2023 at 11:19:34AM +0100, Conor Dooley wrote:
> On Fri, Jul 14, 2023 at 10:00:19AM +0530, Anup Patel wrote:
> 
> > > > OpenSBI v1.3
> > > >    ____                    _____ ____ _____
> > > >   / __ \                  / ____|  _ \_   _|
> > > >  | |  | |_ __   ___ _ __ | (___ | |_) || |
> > > >  | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
> > > >  | |__| | |_) |  __/ | | |____) | |_) || |_
> > > >   \____/| .__/ \___|_| |_|_____/|___/_____|
> > > >         | |
> > > >         |_|
> > > >
> > > > init_coldboot: ipi init failed (error -1009)
> > > >
> > > > Just to note, because we use our own firmware that vendors in OpenSBI
> > > > and compiles only a significantly cut down number of files from it, we
> > > > do not use the fw_dynamic etc flow on our hardware. As a result, we have
> > > > not tested v1.3, nor do we have any immediate plans to change our
> > > > platform firmware to vendor v1.3 either.
> > > >
> > > > I unless there's something obvious to you, it sounds like I will need to
> > > > go and bisect OpenSBI. That's a job for another day though, given the
> > > > time.
> > > >
> > 
> > The real issue is some CPU/HART DT nodes marked as disabled in the
> > DT passed to OpenSBI 1.3.
> > 
> > This issue does not exist in any of the DTs generated by QEMU but some
> > of the DTs in the kernel (such as microchip and SiFive board DTs) have
> > the E-core disabled.
> > 
> > I had discovered this issue in a totally different context after the OpenSBI 1.3
> > release happened. This issue is already fixed in the latest OpenSBI by the
> > following commit c6a35733b74aeff612398f274ed19a74f81d1f37 ("lib: utils:
> > Fix sbi_hartid_to_scratch() usage in ACLINT drivers").
> 
> Great, thanks Anup! I thought I had tested tip-of-tree too, but
> obviously not.
> 
> > I always assumed that Microchip hss.bin is the preferred BIOS for the
> > QEMU microchip-icicle-kit machine but I guess that's not true.
> 
> Unfortunately the HSS has not worked in QEMU for a long time, and while
> I would love to fix it, but am pretty stretched for spare time to begin
> with.
> I usually just do direct kernel boots, which use the OpenSBI that comes
> with QEMU, as I am sure you already know :)
> 
> > At this point, you can either:
> > 1) Use latest OpenSBI on QEMU microchip-icicle-kit machine

I forgot to reply to this point, wondering what should be done with
QEMU. Bumping to v1.3 in QEMU introduces a regression here, regardless
of whether I can go and build a fixed version of OpenSBI.

> > 2) Ensure CPU0 DT node is enabled in DT when booting on QEMU
> >     microchip-icicle-kit machine with OpenSBI 1.3
> 
> Will OpenSBI disable it? If not, I think option 2) needs to be remove
> the DT node. I'll just use tip-of-tree myself & up to the 

Clearly didn't finish this comment. It was meant to say "up to the QEMU
maintainers what they want to do on the QEMU side of things".

Thanks,
Conor.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

  reply	other threads:[~2023-07-14 12:29 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-12 19:01 [PATCH for-8.2 0/7] target/riscv: add 'max' CPU type Daniel Henrique Barboza
2023-07-12 19:01 ` [PATCH for-8.2 1/7] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] Daniel Henrique Barboza
2023-07-12 19:01 ` [PATCH for-8.2 2/7] target/riscv/cpu.c: skip 'bool' check when filtering KVM props Daniel Henrique Barboza
2023-07-12 19:01 ` [PATCH for-8.2 3/7] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[] Daniel Henrique Barboza
2023-07-12 19:01 ` [PATCH for-8.2 4/7] target/riscv/cpu.c: split non-ratified " Daniel Henrique Barboza
2023-07-12 19:01 ` [PATCH for-8.2 5/7] target/riscv/cpu.c: add a ADD_CPU_PROPERTIES_ARRAY() macro Daniel Henrique Barboza
2023-07-12 19:01 ` [PATCH for-8.2 6/7] target/riscv: add 'max' CPU type Daniel Henrique Barboza
2023-07-12 19:22   ` Conor Dooley
2023-07-12 20:30     ` Daniel Henrique Barboza
2023-07-12 21:00       ` Conor Dooley
2023-07-12 21:09         ` Daniel Henrique Barboza
2023-07-12 21:35           ` Conor Dooley
2023-07-12 21:39             ` Daniel Henrique Barboza
2023-07-12 22:14               ` Conor Dooley
2023-07-13 22:12                 ` Boot failure after QEMU's upgrade to OpenSBI v1.3 (was Re: [PATCH for-8.2 6/7] target/riscv: add 'max' CPU type) Conor Dooley
2023-07-13 22:35                   ` Daniel Henrique Barboza
2023-07-13 22:47                     ` Conor Dooley
2023-07-14  1:13                       ` Daniel Henrique Barboza
2023-07-14  3:12                         ` Alistair Francis
2023-07-14  9:26                           ` Daniel Henrique Barboza
2023-07-13 23:04                   ` Conor Dooley
2023-07-14  4:30                   ` Anup Patel
2023-07-14 10:19                     ` Conor Dooley
2023-07-14 12:28                       ` Conor Dooley [this message]
2023-07-15  9:12                         ` Atish Patra
2023-07-19  1:32                           ` Alistair Francis
2023-07-19  5:39                             ` Anup Patel
2023-07-19  9:53                               ` Alistair Francis
2023-07-19 15:21                                 ` Anup Patel
2023-07-19 15:45                                   ` Bin Meng
2023-07-19 16:10                                     ` Anup Patel
2023-07-19 16:18                                       ` Bin Meng
2023-07-19 16:17                                     ` Andreas Schwab
2023-07-19  7:07                             ` Conor Dooley
2023-07-14 12:35                       ` Anup Patel
2023-07-12 19:01 ` [PATCH for-8.2 7/7] avocado, risc-v: add opensbi tests for 'max' CPU Daniel Henrique Barboza

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230714-hash-handwrite-339817b93ba1@spud \
    --to=conor@kernel.org \
    --cc=alistair.francis@wdc.com \
    --cc=anup@brainfault.org \
    --cc=bmeng@tinylab.org \
    --cc=dbarboza@ventanamicro.com \
    --cc=liweiwei@iscas.ac.cn \
    --cc=opensbi@lists.infradead.org \
    --cc=palmer@rivosinc.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=zhiwei_liu@linux.alibaba.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).