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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v16-20020a5d6790000000b003112ab916cdsm19337737wru.73.2023.07.17.05.47.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 05:47:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 0/7] target-arm queue Date: Mon, 17 Jul 2023 13:47:39 +0100 Message-Id: <20230717124746.759085-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org A last small test of bug fixes before rc1. thanks -- PMM The following changes since commit ed8ad9728a9c0eec34db9dff61dfa2f1dd625637: Merge tag 'pull-tpm-2023-07-14-1' of https://github.com/stefanberger/qemu-tpm into staging (2023-07-15 14:54:04 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230717 for you to fetch changes up to c2c1c4a35c7c2b1a4140b0942b9797c857e476a4: hw/nvram: Avoid unnecessary Xilinx eFuse backstore write (2023-07-17 11:05:52 +0100) ---------------------------------------------------------------- target-arm queue: * hw/arm/sbsa-ref: set 'slots' property of xhci * linux-user: Remove pointless NULL check in clock_adjtime handling * ptw: Fix S1_ptw_translate() debug path * ptw: Account for FEAT_RME when applying {N}SW, SA bits * accel/tcg: Zero-pad PC in TCG CPU exec trace lines * hw/nvram: Avoid unnecessary Xilinx eFuse backstore write ---------------------------------------------------------------- Peter Maydell (5): linux-user: Remove pointless NULL check in clock_adjtime handling target/arm/ptw.c: Add comments to S1Translate struct fields target/arm: Fix S1_ptw_translate() debug path target/arm/ptw.c: Account for FEAT_RME when applying {N}SW, SA bits accel/tcg: Zero-pad PC in TCG CPU exec trace lines Tong Ho (1): hw/nvram: Avoid unnecessary Xilinx eFuse backstore write Yuquan Wang (1): hw/arm/sbsa-ref: set 'slots' property of xhci accel/tcg/cpu-exec.c | 4 +-- accel/tcg/translate-all.c | 2 +- hw/arm/sbsa-ref.c | 1 + hw/nvram/xlnx-efuse.c | 11 ++++-- linux-user/syscall.c | 12 +++---- target/arm/ptw.c | 90 +++++++++++++++++++++++++++++++++++++++++------ 6 files changed, 98 insertions(+), 22 deletions(-)