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From: Conor Dooley <conor@kernel.org>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
	alistair.francis@wdc.com, bmeng@tinylab.org,
	liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com,
	palmer@rivosinc.com
Subject: Re: [PATCH for-8.2 0/2] target/riscv: add zicntr and zihpm flags
Date: Tue, 18 Jul 2023 09:23:59 +0100	[thread overview]
Message-ID: <20230718-freedom-subway-0b5d2083b474@spud> (raw)
In-Reply-To: <2f123883-3064-28af-649f-2bbc8c52a60a@ventanamicro.com>

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On Mon, Jul 17, 2023 at 08:11:09PM -0300, Daniel Henrique Barboza wrote:
> On 7/17/23 19:33, Conor Dooley wrote:

> > On Mon, Jul 17, 2023 at 06:54:17PM -0300, Daniel Henrique Barboza wrote:
> > > Hi,
> > > 
> > > I decided to include flags for both timer/counter extensions to make it
> > > easier for us later on when dealing with the RVA22 profile (which
> > > includes both).
> > > 
> > > The features were already implemented by Atish Patra some time ago, but
> > > back then these 2 extensions weren't introduced yet. This means that,
> > > aside from extra stuff in riscv,isa FDT no other functional changes were
> > > made.
> > > 
> > > Both are defaulted to 'true' since QEMU already implements both
> > > features, but the flag can be disabled if Zicsr isn't present or, in
> > > the case of zihpm, if pmu_num = 0.
> > 
> > Out of curiosity, since you are allowing them to be disabled, how do you
> > intend to communicate to a guest that zicsr or zihpm are not present?
> 
> At this point I'd say that existing guests are using other ways of checking
> if these timers and counters are available.

Or they just assume they're there as part of their baseline requirements
;)

> After this patches OSes can confirm
> if these timers are available via riscv,isa, but they can't assume that
> they are not available if riscv,isa doesn't display them.
> 
> There's a chance that guests will continue ignoring these 2 extensions regardless
> of whether the platform exposes them or not.
> 
> > 
> > > This means that,
> > > aside from extra stuff in riscv,isa FDT no other functional changes were
> > > made.
> > 
> > This is barely a "functional" change either, as the presence of these
> > extensions has to be assumed, whether they appear in riscv,isa or not :/
> 
> It's more of an organizational change for the sake of QEMU internals because the
> RVA22 profile happens to include zicntr and zihpm as mandatory extensions. It's
> easier to add the flags than to document why we're claiming RVA22 support but
> aren't displaying these 2 in riscv,isa.

Possibly you should call out ACPI here too, since that does not suffer
from the same issues as riscv,isa in DT, and putting zicntr/zihpm et al
in the ISA string there is needed.

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      reply	other threads:[~2023-07-18  8:24 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-17 21:54 [PATCH for-8.2 0/2] target/riscv: add zicntr and zihpm flags Daniel Henrique Barboza
2023-07-17 21:54 ` [PATCH for-8.2 1/2] target/riscv/cpu.c: add zicntr extension flag Daniel Henrique Barboza
2023-07-24  1:56   ` Alistair Francis
2023-07-17 21:54 ` [PATCH for-8.2 2/2] target/riscv/cpu.c: add zihpm " Daniel Henrique Barboza
2023-07-24  2:00   ` Alistair Francis
2023-07-17 22:33 ` [PATCH for-8.2 0/2] target/riscv: add zicntr and zihpm flags Conor Dooley
2023-07-17 23:11   ` Daniel Henrique Barboza
2023-07-18  8:23     ` Conor Dooley [this message]

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