* [PATCH v2 0/4] Enable CET userspace support
@ 2023-07-20 11:14 Yang Weijiang
2023-07-20 11:14 ` [PATCH v2 1/4] target/i386: Enable XSAVES support for CET states Yang Weijiang
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Yang Weijiang @ 2023-07-20 11:14 UTC (permalink / raw)
To: pbonzini, mtosatti, seanjc, qemu-devel; +Cc: kvm, weijiang.yang
CET virtualization requires VMM userspace setup for CET feature
bits enumeration, this series enables all related settings.
Guest CET user and kernel mode SHSTK/IBT are both supported.
Changes in v2:
1. Added supervisor CET states support.
2. Consolidated all CET states in a struct of vmstate.
v1 link:
https://lore.kernel.org/all/20230421041227.90915-1-weijiang.yang@intel.com/
Yang Weijiang (4):
target/i386: Enable XSAVES support for CET states
target/i386: Add CET MSRs access interface
target/i386: Add CET states to vmstate
target/i386: Advertise CET related flags in feature words
target/i386/cpu.c | 54 +++++++++++++++++++++++++++++----------
target/i386/cpu.h | 41 ++++++++++++++++++++++++++++++
target/i386/kvm/kvm.c | 59 +++++++++++++++++++++++++++++++++++++++++++
target/i386/machine.c | 28 ++++++++++++++++++++
4 files changed, 169 insertions(+), 13 deletions(-)
base-commit: a342ce9dfeed8088c426e5d51d4a7e47f3764b84
--
2.27.0
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 1/4] target/i386: Enable XSAVES support for CET states
2023-07-20 11:14 [PATCH v2 0/4] Enable CET userspace support Yang Weijiang
@ 2023-07-20 11:14 ` Yang Weijiang
2023-07-20 11:14 ` [PATCH v2 2/4] target/i386: Add CET MSRs access interface Yang Weijiang
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Yang Weijiang @ 2023-07-20 11:14 UTC (permalink / raw)
To: pbonzini, mtosatti, seanjc, qemu-devel; +Cc: kvm, weijiang.yang
Add CET_U/S bits in xstate area and report support in xstate
feature mask.
MSR_XSS[bit 11] corresponds to CET user mode states.
MSR_XSS[bit 12] corresponds to CET supervisor mode states.
CET Shadow Stack(SHSTK) and Indirect Branch Tracking(IBT) features
are enumerated via CPUID.(EAX=07H,ECX=0H):ECX[7] and EDX[20]
respectively, two featues share the same state bits in XSS,so
if either of the features is enabled, set CET_U and CET_S bits
together.
Opportunistically fix the array format issue.
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
---
target/i386/cpu.c | 45 ++++++++++++++++++++++++++++++++++++---------
target/i386/cpu.h | 23 +++++++++++++++++++++++
2 files changed, 59 insertions(+), 9 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f083ff4335..ea11b589e3 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -944,8 +944,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.feat_names = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, "cet-u",
+ "cet-s", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
@@ -1421,7 +1421,8 @@ static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
#undef REGISTER
/* CPUID feature bits available in XSS */
-#define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK)
+#define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK | XSTATE_CET_U_MASK | \
+ XSTATE_CET_S_MASK)
ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = {
[XSTATE_FP_BIT] = {
@@ -1439,7 +1440,7 @@ ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = {
.size = sizeof(XSaveAVX) },
[XSTATE_BNDREGS_BIT] =
{ .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
- .size = sizeof(XSaveBNDREG) },
+ .size = sizeof(XSaveBNDREG) },
[XSTATE_BNDCSR_BIT] =
{ .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
.size = sizeof(XSaveBNDCSR) },
@@ -1459,14 +1460,24 @@ ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = {
.feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR,
.offset = 0 /*supervisor mode component, offset = 0 */,
.size = sizeof(XSavesArchLBR) },
+ [XSTATE_CET_U_BIT] = {
+ .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_CET_SHSTK,
+ /*
+ * The features enabled in XSS MSR always use compacted format
+ * to store the data, in this case .offset == 0.
+ */
+ .offset = 0,
+ .size = sizeof(XSavesCETU) },
+ [XSTATE_CET_S_BIT] = {
+ .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_CET_SHSTK,
+ .offset = 0,
+ .size = sizeof(XSavesCETS) },
[XSTATE_XTILE_CFG_BIT] = {
.feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE,
- .size = sizeof(XSaveXTILECFG),
- },
+ .size = sizeof(XSaveXTILECFG) },
[XSTATE_XTILE_DATA_BIT] = {
.feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE,
- .size = sizeof(XSaveXTILEDATA)
- },
+ .size = sizeof(XSaveXTILEDATA) }
};
uint32_t xsave_area_size(uint64_t mask, bool compacted)
@@ -6259,9 +6270,25 @@ static void x86_cpu_enable_xsave_components(X86CPU *cpu)
if (env->features[esa->feature] & esa->bits) {
mask |= (1ULL << i);
}
+
+ /*
+ * Both CET SHSTK and IBT feature depend on XSAVES support, and two
+ * features can be enabled independently, so if either of the two
+ * features is enabled, we set the XSAVES support bits to make the
+ * enabled feature(s) work.
+ */
+ if (i == XSTATE_CET_U_BIT || i == XSTATE_CET_S_BIT) {
+ uint64_t ecx = env->features[FEAT_7_0_ECX];
+ uint64_t edx = env->features[FEAT_7_0_EDX];
+
+ if ((ecx & CPUID_7_0_ECX_CET_SHSTK) ||
+ (edx & CPUID_7_0_EDX_CET_IBT)) {
+ mask |= (1ULL << i);
+ }
+ }
}
- /* Only request permission for first vcpu */
+ /* Only request permission from fisrt vcpu. */
if (kvm_enabled() && !request_perm) {
kvm_request_xsave_components(cpu, mask);
request_perm = true;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index d243e290d3..06855e0926 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -554,6 +554,8 @@ typedef enum X86Seg {
#define XSTATE_ZMM_Hi256_BIT 6
#define XSTATE_Hi16_ZMM_BIT 7
#define XSTATE_PKRU_BIT 9
+#define XSTATE_CET_U_BIT 11
+#define XSTATE_CET_S_BIT 12
#define XSTATE_ARCH_LBR_BIT 15
#define XSTATE_XTILE_CFG_BIT 17
#define XSTATE_XTILE_DATA_BIT 18
@@ -567,6 +569,8 @@ typedef enum X86Seg {
#define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT)
#define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
#define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
+#define XSTATE_CET_U_MASK (1ULL << XSTATE_CET_U_BIT)
+#define XSTATE_CET_S_MASK (1ULL << XSTATE_CET_S_BIT)
#define XSTATE_ARCH_LBR_MASK (1ULL << XSTATE_ARCH_LBR_BIT)
#define XSTATE_XTILE_CFG_MASK (1ULL << XSTATE_XTILE_CFG_BIT)
#define XSTATE_XTILE_DATA_MASK (1ULL << XSTATE_XTILE_DATA_BIT)
@@ -841,6 +845,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
#define CPUID_7_0_ECX_WAITPKG (1U << 5)
/* Additional AVX-512 Vector Byte Manipulation Instruction */
#define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6)
+/* CET SHSTK feature */
+#define CPUID_7_0_ECX_CET_SHSTK (1U << 7)
/* Galois Field New Instructions */
#define CPUID_7_0_ECX_GFNI (1U << 8)
/* Vector AES Instructions */
@@ -884,6 +890,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
#define CPUID_7_0_EDX_TSX_LDTRK (1U << 16)
/* Architectural LBRs */
#define CPUID_7_0_EDX_ARCH_LBR (1U << 19)
+/* CET IBT feature */
+#define CPUID_7_0_EDX_CET_IBT (1U << 20)
/* AMX_BF16 instruction */
#define CPUID_7_0_EDX_AMX_BF16 (1U << 22)
/* AVX512_FP16 instruction */
@@ -1428,6 +1436,19 @@ typedef struct XSavePKRU {
uint32_t padding;
} XSavePKRU;
+/* Ext. save area 11: User mode CET state */
+typedef struct XSavesCETU {
+ uint64_t u_cet;
+ uint64_t user_ssp;
+} XSavesCETU;
+
+/* Ext. save area 12: Supervisor mode CET state */
+typedef struct XSavesCETS {
+ uint64_t pl0_ssp;
+ uint64_t pl1_ssp;
+ uint64_t pl2_ssp;
+} XSavesCETS;
+
/* Ext. save area 17: AMX XTILECFG state */
typedef struct XSaveXTILECFG {
uint8_t xtilecfg[64];
@@ -1463,6 +1484,8 @@ QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
+QEMU_BUILD_BUG_ON(sizeof(XSavesCETU) != 0x10);
+QEMU_BUILD_BUG_ON(sizeof(XSavesCETS) != 0x18);
QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) != 0x40);
QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) != 0x2000);
QEMU_BUILD_BUG_ON(sizeof(XSavesArchLBR) != 0x328);
--
2.27.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 2/4] target/i386: Add CET MSRs access interface
2023-07-20 11:14 [PATCH v2 0/4] Enable CET userspace support Yang Weijiang
2023-07-20 11:14 ` [PATCH v2 1/4] target/i386: Enable XSAVES support for CET states Yang Weijiang
@ 2023-07-20 11:14 ` Yang Weijiang
2023-07-20 11:14 ` [PATCH v2 3/4] target/i386: Add CET states to vmstate Yang Weijiang
2023-07-20 11:14 ` [PATCH v2 4/4] target/i386: Advertise CET related flags in feature words Yang Weijiang
3 siblings, 0 replies; 5+ messages in thread
From: Yang Weijiang @ 2023-07-20 11:14 UTC (permalink / raw)
To: pbonzini, mtosatti, seanjc, qemu-devel; +Cc: kvm, weijiang.yang
CET MSRs include:
MSR_IA32_U_CET - user mode CET control bits.
MSR_IA32_S_CET - supervisor mode CET control bits.
MSR_IA32_PL{0,1,2,3}_SSP - linear addresses of SSPs for user/kernel modes.
MSR_IA32_SSP_TBL_ADDR - linear address of interrupt SSP table
MSR_KVM_GUEST_SSP - current shadow stack pointer
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
---
target/i386/cpu.h | 18 +++++++++++++
target/i386/kvm/kvm.c | 59 +++++++++++++++++++++++++++++++++++++++++++
2 files changed, 77 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 06855e0926..ef1f3d6138 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -545,6 +545,15 @@ typedef enum X86Seg {
#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
#define MSR_IA32_VMX_VMFUNC 0x00000491
+#define MSR_IA32_U_CET 0x000006a0
+#define MSR_IA32_S_CET 0x000006a2
+#define MSR_IA32_PL0_SSP 0x000006a4
+#define MSR_IA32_PL1_SSP 0x000006a5
+#define MSR_IA32_PL2_SSP 0x000006a6
+#define MSR_IA32_PL3_SSP 0x000006a7
+#define MSR_IA32_SSP_TBL_ADDR 0x000006a8
+#define MSR_KVM_GUEST_SSP 0x4b564d09
+
#define XSTATE_FP_BIT 0
#define XSTATE_SSE_BIT 1
#define XSTATE_YMM_BIT 2
@@ -1766,6 +1775,15 @@ typedef struct CPUArchState {
uintptr_t retaddr;
+ uint64_t u_cet;
+ uint64_t s_cet;
+ uint64_t pl0_ssp;
+ uint64_t pl1_ssp;
+ uint64_t pl2_ssp;
+ uint64_t pl3_ssp;
+ uint64_t ssp_table_addr;
+ uint64_t guest_ssp;
+
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index de531842f6..ab3a755b97 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -3591,6 +3591,24 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
env->msr_ia32_sgxlepubkeyhash[3]);
}
+ if ((env->features[FEAT_XSAVE_XSS_LO] & XSTATE_CET_U_MASK) &&
+ (env->features[FEAT_XSAVE_XSS_LO] & XSTATE_CET_S_MASK)) {
+ if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) {
+ kvm_msr_entry_add(cpu, MSR_IA32_U_CET, env->u_cet);
+ kvm_msr_entry_add(cpu, MSR_IA32_S_CET, env->s_cet);
+ kvm_msr_entry_add(cpu, MSR_KVM_GUEST_SSP, env->guest_ssp);
+ kvm_msr_entry_add(cpu, MSR_IA32_PL0_SSP, env->pl0_ssp);
+ kvm_msr_entry_add(cpu, MSR_IA32_PL1_SSP, env->pl1_ssp);
+ kvm_msr_entry_add(cpu, MSR_IA32_PL2_SSP, env->pl2_ssp);
+ kvm_msr_entry_add(cpu, MSR_IA32_PL3_SSP, env->pl3_ssp);
+ kvm_msr_entry_add(cpu, MSR_IA32_SSP_TBL_ADDR,
+ env->ssp_table_addr);
+ } else if (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT) {
+ kvm_msr_entry_add(cpu, MSR_IA32_U_CET, env->u_cet);
+ kvm_msr_entry_add(cpu, MSR_IA32_S_CET, env->s_cet);
+ }
+ }
+
if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
kvm_msr_entry_add(cpu, MSR_IA32_XFD,
env->msr_xfd);
@@ -4024,6 +4042,23 @@ static int kvm_get_msrs(X86CPU *cpu)
kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, 0);
}
+ if ((env->features[FEAT_XSAVE_XSS_LO] & XSTATE_CET_U_MASK) &&
+ (env->features[FEAT_XSAVE_XSS_LO] & XSTATE_CET_S_MASK)) {
+ if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) {
+ kvm_msr_entry_add(cpu, MSR_IA32_U_CET, 0);
+ kvm_msr_entry_add(cpu, MSR_IA32_S_CET, 0);
+ kvm_msr_entry_add(cpu, MSR_KVM_GUEST_SSP, 0);
+ kvm_msr_entry_add(cpu, MSR_IA32_PL0_SSP, 0);
+ kvm_msr_entry_add(cpu, MSR_IA32_PL1_SSP, 0);
+ kvm_msr_entry_add(cpu, MSR_IA32_PL2_SSP, 0);
+ kvm_msr_entry_add(cpu, MSR_IA32_PL3_SSP, 0);
+ kvm_msr_entry_add(cpu, MSR_IA32_SSP_TBL_ADDR, 0);
+ } else if (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT) {
+ kvm_msr_entry_add(cpu, MSR_IA32_U_CET, 0);
+ kvm_msr_entry_add(cpu, MSR_IA32_S_CET, 0);
+ }
+ }
+
if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
kvm_msr_entry_add(cpu, MSR_IA32_XFD, 0);
kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR, 0);
@@ -4346,6 +4381,30 @@ static int kvm_get_msrs(X86CPU *cpu)
env->msr_ia32_sgxlepubkeyhash[index - MSR_IA32_SGXLEPUBKEYHASH0] =
msrs[i].data;
break;
+ case MSR_IA32_U_CET:
+ env->u_cet = msrs[i].data;
+ break;
+ case MSR_IA32_S_CET:
+ env->s_cet = msrs[i].data;
+ break;
+ case MSR_KVM_GUEST_SSP:
+ env->guest_ssp = msrs[i].data;
+ break;
+ case MSR_IA32_PL0_SSP:
+ env->pl0_ssp = msrs[i].data;
+ break;
+ case MSR_IA32_PL1_SSP:
+ env->pl1_ssp = msrs[i].data;
+ break;
+ case MSR_IA32_PL2_SSP:
+ env->pl2_ssp = msrs[i].data;
+ break;
+ case MSR_IA32_PL3_SSP:
+ env->pl3_ssp = msrs[i].data;
+ break;
+ case MSR_IA32_SSP_TBL_ADDR:
+ env->ssp_table_addr = msrs[i].data;
+ break;
case MSR_IA32_XFD:
env->msr_xfd = msrs[i].data;
break;
--
2.27.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 3/4] target/i386: Add CET states to vmstate
2023-07-20 11:14 [PATCH v2 0/4] Enable CET userspace support Yang Weijiang
2023-07-20 11:14 ` [PATCH v2 1/4] target/i386: Enable XSAVES support for CET states Yang Weijiang
2023-07-20 11:14 ` [PATCH v2 2/4] target/i386: Add CET MSRs access interface Yang Weijiang
@ 2023-07-20 11:14 ` Yang Weijiang
2023-07-20 11:14 ` [PATCH v2 4/4] target/i386: Advertise CET related flags in feature words Yang Weijiang
3 siblings, 0 replies; 5+ messages in thread
From: Yang Weijiang @ 2023-07-20 11:14 UTC (permalink / raw)
To: pbonzini, mtosatti, seanjc, qemu-devel; +Cc: kvm, weijiang.yang
Add CET states in vmstate if the feature is enabled.
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
---
target/i386/machine.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/target/i386/machine.c b/target/i386/machine.c
index c7ac8084b2..6d42f6dc7e 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -1586,6 +1586,33 @@ static const VMStateDescription vmstate_arch_lbr = {
}
};
+static bool cet_needed(void *opaque)
+{
+ X86CPU *cpu = opaque;
+ CPUX86State *env = &cpu->env;
+
+ return !!((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) ||
+ (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT));
+}
+
+static const VMStateDescription vmstate_cet = {
+ .name = "cpu/cet",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = cet_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(env.u_cet, X86CPU),
+ VMSTATE_UINT64(env.s_cet, X86CPU),
+ VMSTATE_UINT64(env.guest_ssp, X86CPU),
+ VMSTATE_UINT64(env.pl0_ssp, X86CPU),
+ VMSTATE_UINT64(env.pl1_ssp, X86CPU),
+ VMSTATE_UINT64(env.pl2_ssp, X86CPU),
+ VMSTATE_UINT64(env.pl3_ssp, X86CPU),
+ VMSTATE_UINT64(env.ssp_table_addr, X86CPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static bool triple_fault_needed(void *opaque)
{
X86CPU *cpu = opaque;
@@ -1745,6 +1772,7 @@ const VMStateDescription vmstate_x86_cpu = {
&vmstate_msr_tsx_ctrl,
&vmstate_msr_intel_sgx,
&vmstate_pdptrs,
+ &vmstate_cet,
&vmstate_msr_xfd,
#ifdef TARGET_X86_64
&vmstate_amx_xtile,
--
2.27.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 4/4] target/i386: Advertise CET related flags in feature words
2023-07-20 11:14 [PATCH v2 0/4] Enable CET userspace support Yang Weijiang
` (2 preceding siblings ...)
2023-07-20 11:14 ` [PATCH v2 3/4] target/i386: Add CET states to vmstate Yang Weijiang
@ 2023-07-20 11:14 ` Yang Weijiang
3 siblings, 0 replies; 5+ messages in thread
From: Yang Weijiang @ 2023-07-20 11:14 UTC (permalink / raw)
To: pbonzini, mtosatti, seanjc, qemu-devel; +Cc: kvm, weijiang.yang
Add SHSTK and IBT flags in feature words with entry/exit
control flags.
CET SHSTK and IBT feature are enumerated via CPUID(EAX=7,ECX=0)
ECX[bit 7] and EDX[bit 20]. CET states load/restore at vmentry/
vmexit are controlled by VMX_ENTRY_CTLS[bit 20] and VMX_EXIT_CTLS[bit 28].
Enable these flags so that KVM can enumerate the features properly.
CET feature is only available on platforms with IA32_VMX_BASIC[bit 56]
set, otherwise, CET features are disabled in KVM.
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
---
target/i386/cpu.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ea11b589e3..79a90e35bf 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -835,7 +835,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
NULL, "avx512vbmi", "umip", "pku",
- NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
+ NULL /* ospke */, "waitpkg", "avx512vbmi2", "shstk",
"gfni", "vaes", "vpclmulqdq", "avx512vnni",
"avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
"la57", NULL, NULL, NULL,
@@ -858,7 +858,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"avx512-vp2intersect", NULL, "md-clear", NULL,
NULL, NULL, "serialize", NULL,
"tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr",
- NULL, NULL, "amx-bf16", "avx512-fp16",
+ "ibt", NULL, "amx-bf16", "avx512-fp16",
"amx-tile", "amx-int8", "spec-ctrl", "stibp",
NULL, "arch-capabilities", "core-capability", "ssbd",
},
@@ -1120,7 +1120,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"vmx-exit-save-efer", "vmx-exit-load-efer",
"vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
- NULL, "vmx-exit-load-pkrs", NULL, NULL,
+ "vmx-exit-save-cet-ctl", "vmx-exit-load-pkrs", NULL, NULL,
},
.msr = {
.index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
@@ -1135,7 +1135,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, "vmx-entry-ia32e-mode", NULL, NULL,
NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
"vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
- NULL, NULL, "vmx-entry-load-pkrs", NULL,
+ "vmx-entry-load-cet-ctl", NULL, "vmx-entry-load-pkrs", NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
@@ -1192,6 +1192,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.feat_names = {
[54] = "vmx-ins-outs",
[55] = "vmx-true-ctls",
+ [56] = "vmx-hw-no-errcode",
},
.msr = {
.index = MSR_IA32_VMX_BASIC,
--
2.27.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-07-20 14:21 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-07-20 11:14 [PATCH v2 0/4] Enable CET userspace support Yang Weijiang
2023-07-20 11:14 ` [PATCH v2 1/4] target/i386: Enable XSAVES support for CET states Yang Weijiang
2023-07-20 11:14 ` [PATCH v2 2/4] target/i386: Add CET MSRs access interface Yang Weijiang
2023-07-20 11:14 ` [PATCH v2 3/4] target/i386: Add CET states to vmstate Yang Weijiang
2023-07-20 11:14 ` [PATCH v2 4/4] target/i386: Advertise CET related flags in feature words Yang Weijiang
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