From: Nicholas Piggin <npiggin@gmail.com>
To: Daniel Henrique Barboza <danielhb413@gmail.com>
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
"Cédric Le Goater" <clg@kaod.org>,
"Frédéric Barrat" <fbarrat@linux.ibm.com>,
"David Gibson" <david@gibson.dropbear.id.au>,
"Greg Kurz" <groug@kaod.org>,
"Harsh Prateek Bora" <harshpb@linux.ibm.com>,
qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
qemu-stable@nongnu.org
Subject: [PATCH 2/2] target/ppc: Fix VRMA page size for ISA v3.0
Date: Fri, 21 Jul 2023 15:02:55 +1000 [thread overview]
Message-ID: <20230721050255.100090-3-npiggin@gmail.com> (raw)
In-Reply-To: <20230721050255.100090-1-npiggin@gmail.com>
Until v2.07s, the VRMA page size (L||LP) was encoded in LPCR[VRMASD].
In v3.0 that moved to the partition table PS field.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/mmu-hash64.c | 41 +++++++++++++++++++++++++++++++++++------
1 file changed, 35 insertions(+), 6 deletions(-)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index a0c90df3ce..bda0ba90ea 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -874,12 +874,41 @@ static target_ulong rmls_limit(PowerPCCPU *cpu)
return rma_sizes[rmls];
}
-static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb)
+/* Return the LLP in SLB_VSID format */
+static uint64_t get_vrma_llp(PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
- target_ulong lpcr = env->spr[SPR_LPCR];
- uint32_t vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT;
- target_ulong vsid = SLB_VSID_VRMA | ((vrmasd << 4) & SLB_VSID_LLP_MASK);
+ uint64_t llp;
+
+ if (env->mmu_model == POWERPC_MMU_3_00) {
+ ppc_v3_pate_t pate;
+ uint64_t ps;
+
+ /*
+ * ISA v3.0 removes the LPCR[VRMASD] field and puts the VRMA base
+ * page size (L||LP equivalent) in the PS field in the HPT partition
+ * table entry.
+ */
+ if (!ppc64_v3_get_pate(cpu, cpu->env.spr[SPR_LPIDR], &pate)) {
+ error_report("Bad VRMA with no partition table entry\n");
+ return 0;
+ }
+ ps = pate.dw0 >> (63 - 58);
+ llp = ((ps & 0x4) << (63 - 55 - 2)) | ((ps & 0x3) << (63 - 59));
+
+ } else {
+ uint64_t lpcr = env->spr[SPR_LPCR];
+ target_ulong vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT;
+
+ llp = (vrmasd << 4) & SLB_VSID_LLP_MASK;
+ }
+
+ return llp;
+}
+
+static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb)
+{
+ target_ulong vsid = SLB_VSID_VRMA | get_vrma_llp(cpu);
int i;
for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
@@ -897,8 +926,8 @@ static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb)
}
}
- error_report("Bad page size encoding in LPCR[VRMASD]; LPCR=0x"
- TARGET_FMT_lx, lpcr);
+ error_report("Bad VRMA page size encoding 0x" TARGET_FMT_lx,
+ get_vrma_llp(cpu));
return -1;
}
--
2.40.1
next prev parent reply other threads:[~2023-07-21 5:04 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-21 5:02 [PATCH 0/2] target/ppc: Fixes for hash MMU for ISA v3.0 Nicholas Piggin
2023-07-21 5:02 ` [PATCH 1/2] target/ppc: Implement ASDR register for ISA v3.0 for HPT Nicholas Piggin
2023-07-21 5:02 ` Nicholas Piggin [this message]
2023-07-21 7:27 ` [PATCH 0/2] target/ppc: Fixes for hash MMU for ISA v3.0 Cédric Le Goater
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