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[213.175.37.10]) by smtp.gmail.com with ESMTPSA id q1-20020adfcd81000000b003140fff4f75sm8108722wrj.17.2023.07.24.08.32.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jul 2023 08:32:55 -0700 (PDT) Date: Mon, 24 Jul 2023 17:32:54 +0200 From: Igor Mammedov To: Sunil V L Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, "Michael S . Tsirkin" , Ani Sinha , Peter Maydell , Shannon Zhao , Paolo Bonzini , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Andrew Jones , Anup Patel Subject: Re: [PATCH 04/10] hw/riscv: virt: Add PCIe HIGHMEM in memmap Message-ID: <20230724173254.3423a204@imammedo.users.ipa.redhat.com> In-Reply-To: <20230712163943.98994-5-sunilvl@ventanamicro.com> References: <20230712163943.98994-1-sunilvl@ventanamicro.com> <20230712163943.98994-5-sunilvl@ventanamicro.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, 12 Jul 2023 22:09:37 +0530 Sunil V L wrote: > PCIe High MMIO base is actually dynamic and fixed at > run time based on the RAM configured. Currently, this is > not part of the memmap and kept in separate static variable > in virt.c. However, ACPI code also needs this information > to populate DSDT. So, once the base is discovered, merge > this into the final memmap which can be used to create > ACPI tables later. can ACPI code fetch virt_high_pcie_memmap at runtime from host bridge (like we do in pc/q35)? > Signed-off-by: Sunil V L > --- > hw/riscv/virt.c | 31 ++++++++++++++++++++++++++++++- > include/hw/riscv/virt.h | 9 +++++++-- > 2 files changed, 37 insertions(+), 3 deletions(-) > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index f6067db8ec..7aee06f021 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -84,6 +84,22 @@ static const MemMapEntry virt_memmap[] = { > > static MemMapEntry virt_high_pcie_memmap; > > +/* > + * virt_memmap doesn't include floating High Mem IO address entry. To enable > + * code organization in multiple files (ex: ACPI), it is better to have single > + * memmap which has complete information. > + * > + * VIRT_HIGH_PCIE_MMIO is always greater than the last memmap entry and hence > + * full_virt_memmap is capable of holding both virt_memmap and > + * VIRT_HIGH_PCIE_MMIO entry. > + * > + * The values for these floating entries will be updated when top of RAM is > + * discovered. > + */ > +static MemMapEntry full_virt_memmap[] = { > + [VIRT_HIGH_PCIE_MMIO] = { 0x0, 0 }, > +}; > + > #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) > > static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, > @@ -1444,7 +1460,20 @@ static void virt_machine_init(MachineState *machine) > ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); > } > > - s->memmap = virt_memmap; > + /* > + * Initialize the floating values in full memory map > + */ > + full_virt_memmap[VIRT_HIGH_PCIE_MMIO].base = virt_high_pcie_memmap.base; > + full_virt_memmap[VIRT_HIGH_PCIE_MMIO].size = virt_high_pcie_memmap.size; > + > + s->memmap = full_virt_memmap; > + /* > + * Copy the base virt_memmap entries to full memmap > + */ > + for (i = 0; i < ARRAY_SIZE(virt_memmap); i++) { > + s->memmap[i] = virt_memmap[i]; > + } > + > > /* register system main memory (actual RAM) */ > memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, > diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h > index 00c22492a7..1d7ddf5df0 100644 > --- a/include/hw/riscv/virt.h > +++ b/include/hw/riscv/virt.h > @@ -60,7 +60,7 @@ struct RISCVVirtState { > char *oem_id; > char *oem_table_id; > OnOffAuto acpi; > - const MemMapEntry *memmap; > + MemMapEntry *memmap; > PCIBus *bus; > }; > > @@ -84,7 +84,12 @@ enum { > VIRT_PCIE_MMIO, > VIRT_PCIE_PIO, > VIRT_PLATFORM_BUS, > - VIRT_PCIE_ECAM > + VIRT_PCIE_ECAM, > + VIRT_LAST_MEMMAP /* Keep this entry always last */ > +}; > + > +enum { > + VIRT_HIGH_PCIE_MMIO = VIRT_LAST_MEMMAP, > }; > > enum {