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[213.175.37.10]) by smtp.gmail.com with ESMTPSA id u27-20020a1709063b9b00b0098e42bef732sm1933226ejf.183.2023.07.28.04.55.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jul 2023 04:55:21 -0700 (PDT) Date: Fri, 28 Jul 2023 13:55:20 +0200 From: Igor Mammedov To: xianglai li Cc: qemu-devel@nongnu.org, Xiaojuan Yang , Song Gao , "Michael S. Tsirkin" , Ani Sinha , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum , Philippe =?UTF-8?B?TWF0aGlldS1EYXVkw6k=?= , Yanan Wang , "Daniel P. =?UTF-8?B?QmVycmFuZ8Op?=" , Peter Xu , David Hildenbrand Subject: Re: [PATCH 2/8] Update CPUs AML with cpu-(ctrl)dev change Message-ID: <20230728135520.3c79fae7@imammedo.users.ipa.redhat.com> In-Reply-To: References: X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=170.10.133.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, 20 Jul 2023 15:15:07 +0800 xianglai li wrote: > CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is ba= sed on > PCI and is IO port based and hence existing cpus AML code assumes _CRS ob= jects > would evaluate to a system resource which describes IO Port address. But = on LOONGARCH > arch CPUs control device(\\_SB.PRES) register interface is memory-mapped = hence > _CRS object should evaluate to system resource which describes memory-map= ped > base address. >=20 > This cpus AML code change updates the existing inerface of the build cpus= AML ^^^ typo > function to accept both IO/MEMORY type regions and update the _CRS object > correspondingly. try to reformat commit message to less than 80 character per line >=20 > Cc: Xiaojuan Yang > Cc: Song Gao > Cc: "Michael S. Tsirkin" > Cc: Igor Mammedov > Cc: Ani Sinha > Cc: Paolo Bonzini > Cc: Richard Henderson > Cc: Eduardo Habkost > Cc: Marcel Apfelbaum > Cc: "Philippe Mathieu-Daud=C3=A9" > Cc: Yanan Wang > Cc: "Daniel P. Berrang=C3=A9" > Cc: Peter Xu > Cc: David Hildenbrand > Signed-off-by: xianglai li > --- > hw/acpi/cpu.c | 30 +++++++++++++++++++++++------- > hw/i386/acpi-build.c | 2 +- > include/hw/acpi/cpu.h | 5 +++-- > 3 files changed, 27 insertions(+), 10 deletions(-) >=20 > diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c > index 6897c8789a..3b945a1a40 100644 > --- a/hw/acpi/cpu.c > +++ b/hw/acpi/cpu.c > @@ -5,6 +5,7 @@ > #include "qapi/qapi-events-acpi.h" > #include "trace.h" > #include "sysemu/numa.h" > +#include "hw/acpi/cpu_hotplug.h" > =20 > #define OVMF_CPUHP_SMI_CMD 4 > =20 > @@ -331,9 +332,10 @@ const VMStateDescription vmstate_cpu_hotplug =3D { > #define CPU_FW_EJECT_EVENT "CEJF" > =20 > void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeature= s opts, > - hwaddr io_base, > + hwaddr mmap_io_base, > const char *res_root, > - const char *event_handler_method) > + const char *event_handler_method, > + AmlRegionSpace rs) > { > Aml *ifctx; > Aml *field; > @@ -360,14 +362,28 @@ void build_cpus_aml(Aml *table, MachineState *machi= ne, CPUHotplugFeatures opts, > aml_append(cpu_ctrl_dev, aml_mutex(CPU_LOCK, 0)); > =20 > crs =3D aml_resource_template(); > - aml_append(crs, aml_io(AML_DECODE16, io_base, io_base, 1, > + if (rs =3D=3D AML_SYSTEM_IO) { > + aml_append(crs, aml_io(AML_DECODE16, mmap_io_base, mmap_io_b= ase, 1, > ACPI_CPU_HOTPLUG_REG_LEN)); > + } else { > + aml_append(crs, aml_memory32_fixed(mmap_io_base, > + ACPI_CPU_HOTPLUG_REG_LEN, AML_READ_WRITE)= ); > + } > aml_append(cpu_ctrl_dev, aml_name_decl("_CRS", crs)); > =20 > - /* declare CPU hotplug MMIO region with related access fields */ > - aml_append(cpu_ctrl_dev, > - aml_operation_region("PRST", AML_SYSTEM_IO, aml_int(io_base), > - ACPI_CPU_HOTPLUG_REG_LEN)); > + if (rs =3D=3D AML_SYSTEM_IO) { > + /* declare CPU hotplug MMIO region with related access field= s */ > + aml_append(cpu_ctrl_dev, > + aml_operation_region("PRST", AML_SYSTEM_IO, > + aml_int(mmap_io_base), > + ACPI_CPU_HOTPLUG_REG_LEN)); > + } else { > + aml_append(cpu_ctrl_dev, > + aml_operation_region("PRST", AML_SYSTEM_MEMORY, > + aml_int(mmap_io_base), > + ACPI_CPU_HOTPLUG_REG_LEN)); > + } to reduce duplication, following could be better way to spell it: g_assert(rs =3D=3D foo1 || rs =3D=3D foo2) ... aml_operation_region("PRST", rs, aml_int(io_base), ... > =20 > field =3D aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, > AML_WRITE_AS_ZEROS); > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > index 9c74fa17ad..5d02690593 100644 > --- a/hw/i386/acpi-build.c > +++ b/hw/i386/acpi-build.c > @@ -1548,7 +1548,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > .fw_unplugs_cpu =3D pm->smi_on_cpu_unplug, > }; > build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, > - "\\_SB.PCI0", "\\_GPE._E02"); > + "\\_SB.PCI0", "\\_GPE._E02", AML_SYSTEM_IO); > } > =20 > if (pcms->memhp_io_base && nr_mem) { > diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h > index 999caaf510..cddea78333 100644 > --- a/include/hw/acpi/cpu.h > +++ b/include/hw/acpi/cpu.h > @@ -56,9 +56,10 @@ typedef struct CPUHotplugFeatures { > } CPUHotplugFeatures; > =20 > void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeature= s opts, > - hwaddr io_base, > + hwaddr mmap_io_base, > const char *res_root, > - const char *event_handler_method); > + const char *event_handler_method, > + AmlRegionSpace rs); > =20 > void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList ***li= st); > =20