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[213.175.37.10]) by smtp.gmail.com with ESMTPSA id b12-20020a170906038c00b00991faf3810esm2110586eja.146.2023.07.28.06.23.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jul 2023 06:23:29 -0700 (PDT) Date: Fri, 28 Jul 2023 15:23:28 +0200 From: Igor Mammedov To: xianglai li Cc: qemu-devel@nongnu.org, Xiaojuan Yang , Song Gao , "Michael S. Tsirkin" , Ani Sinha , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum , Philippe =?UTF-8?B?TWF0aGlldS1EYXVkw6k=?= , Yanan Wang , "Daniel P. =?UTF-8?B?QmVycmFuZ8Op?=" , Peter Xu , David Hildenbrand Subject: Re: [PATCH 6/8] Add support of *unrealize* for loongarch cpu Message-ID: <20230728152328.37420bee@imammedo.users.ipa.redhat.com> In-Reply-To: <3c03a7e5c3a3e93adb50b852264a02790221865e.1689837093.git.lixianglai@loongson.cn> References: <3c03a7e5c3a3e93adb50b852264a02790221865e.1689837093.git.lixianglai@loongson.cn> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=170.10.129.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, 20 Jul 2023 15:15:11 +0800 xianglai li wrote: > 1.Add the Unrealize function to the Loongarch CPU for cpu hot-(un)plug > 2.Add CPU topology-related properties to the Loongarch CPU for cpu hot-(u= n)plug >=20 > Cc: Xiaojuan Yang > Cc: Song Gao > Cc: "Michael S. Tsirkin" > Cc: Igor Mammedov > Cc: Ani Sinha > Cc: Paolo Bonzini > Cc: Richard Henderson > Cc: Eduardo Habkost > Cc: Marcel Apfelbaum > Cc: "Philippe Mathieu-Daud=C3=A9" > Cc: Yanan Wang > Cc: "Daniel P. Berrang=C3=A9" > Cc: Peter Xu > Cc: David Hildenbrand > Signed-off-by: xianglai li > --- > target/loongarch/cpu.c | 33 +++++++++++++++++++++++++++++++++ > target/loongarch/cpu.h | 1 + > 2 files changed, 34 insertions(+) >=20 > diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c > index ad93ecac92..97c577820f 100644 > --- a/target/loongarch/cpu.c > +++ b/target/loongarch/cpu.c > @@ -18,6 +18,7 @@ > #include "cpu-csr.h" > #include "sysemu/reset.h" > #include "tcg/tcg.h" > +#include "hw/qdev-properties.h" > =20 > const char * const regnames[32] =3D { > "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", > @@ -540,6 +541,24 @@ static void loongarch_cpu_realizefn(DeviceState *dev= , Error **errp) > lacc->parent_realize(dev, errp); > } > =20 > +static void loongarch_cpu_unrealizefn(DeviceState *dev) > +{ > + LoongArchCPUClass *mcc =3D LOONGARCH_CPU_GET_CLASS(dev); > + > +#ifndef CONFIG_USER_ONLY > + CPUState *cs =3D CPU(dev); > + LoongArchCPU *cpu =3D LOONGARCH_CPU(dev); > + CPULoongArchState *env =3D &cpu->env; > + > + cpu_remove_sync(CPU(dev)); > + cpu_address_space_destroy(cs, 0); > + address_space_destroy(&env->address_space_iocsr); > + memory_region_del_subregion(&env->system_iocsr, &env->iocsr_mem); > +#endif > + > + mcc->parent_unrealize(dev); > +} > + > #ifndef CONFIG_USER_ONLY > static void loongarch_qemu_write(void *opaque, hwaddr addr, > uint64_t val, unsigned size) > @@ -697,6 +716,15 @@ static gchar *loongarch_gdb_arch_name(CPUState *cs) > return g_strdup("loongarch64"); > } > =20 > +static Property loongarch_cpu_properties[] =3D { > + DEFINE_PROP_INT32("socket-id", LoongArchCPU, socket_id, 0), > + DEFINE_PROP_INT32("core-id", LoongArchCPU, core_id, 0), > + DEFINE_PROP_INT32("thread-id", LoongArchCPU, thread_id, 0), > + DEFINE_PROP_INT32("node-id", LoongArchCPU, node_id, CPU_UNSET_NUMA_N= ODE_ID), > + > + DEFINE_PROP_END_OF_LIST() > +}; this should be a part of topo patches > + > static void loongarch_cpu_class_init(ObjectClass *c, void *data) > { > LoongArchCPUClass *lacc =3D LOONGARCH_CPU_CLASS(c); > @@ -704,8 +732,12 @@ static void loongarch_cpu_class_init(ObjectClass *c,= void *data) > DeviceClass *dc =3D DEVICE_CLASS(c); > ResettableClass *rc =3D RESETTABLE_CLASS(c); > =20 > + device_class_set_props(dc, loongarch_cpu_properties); > device_class_set_parent_realize(dc, loongarch_cpu_realizefn, > &lacc->parent_realize); > + device_class_set_parent_unrealize(dc, loongarch_cpu_unrealizefn, > + &lacc->parent_unrealize); > + > resettable_class_set_parent_phases(rc, NULL, loongarch_cpu_reset_hol= d, NULL, > &lacc->parent_phases); > =20 > @@ -730,6 +762,7 @@ static void loongarch_cpu_class_init(ObjectClass *c, = void *data) > #ifdef CONFIG_TCG > cc->tcg_ops =3D &loongarch_tcg_ops; > #endif > + dc->user_creatable =3D true; > } > =20 > #define DEFINE_LOONGARCH_CPU_TYPE(model, initfn) \ > diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h > index f4439c245f..32feee4fe6 100644 > --- a/target/loongarch/cpu.h > +++ b/target/loongarch/cpu.h > @@ -397,6 +397,7 @@ struct LoongArchCPUClass { > /*< public >*/ > =20 > DeviceRealize parent_realize; > + DeviceUnrealize parent_unrealize; > ResettablePhases parent_phases; > }; > =20