From: Thomas Huth <thuth@redhat.com>
To: "Michael S. Tsirkin" <mst@redhat.com>, Peter Xu <peterx@redhat.com>
Cc: "Jason Wang" <jasowang@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
qemu-devel@nongnu.org,
"Daniel P . Berrangé" <berrange@redhat.com>,
qemu-stable@nongnu.org, "Paolo Bonzini" <pbonzini@redhat.com>
Subject: [PATCH 3/6] hw/i386/intel_iommu: Fix struct VTDInvDescIEC on big endian hosts
Date: Wed, 2 Aug 2023 15:57:20 +0200 [thread overview]
Message-ID: <20230802135723.178083-4-thuth@redhat.com> (raw)
In-Reply-To: <20230802135723.178083-1-thuth@redhat.com>
On big endian hosts, we need to reverse the bitfield order in the
struct VTDInvDescIEC, just like it is already done for the other
bitfields in the various structs of the intel-iommu device.
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
hw/i386/intel_iommu_internal.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 2e61eec2f5..e1450c5cfe 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -321,12 +321,21 @@ typedef enum VTDFaultReason {
/* Interrupt Entry Cache Invalidation Descriptor: VT-d 6.5.2.7. */
struct VTDInvDescIEC {
+#if HOST_BIG_ENDIAN
+ uint64_t reserved_2:16;
+ uint64_t index:16; /* Start index to invalidate */
+ uint64_t index_mask:5; /* 2^N for continuous int invalidation */
+ uint64_t resved_1:22;
+ uint64_t granularity:1; /* If set, it's global IR invalidation */
+ uint64_t type:4; /* Should always be 0x4 */
+#else
uint32_t type:4; /* Should always be 0x4 */
uint32_t granularity:1; /* If set, it's global IR invalidation */
uint32_t resved_1:22;
uint32_t index_mask:5; /* 2^N for continuous int invalidation */
uint32_t index:16; /* Start index to invalidate */
uint32_t reserved_2:16;
+#endif
};
typedef struct VTDInvDescIEC VTDInvDescIEC;
--
2.39.3
next prev parent reply other threads:[~2023-08-02 13:59 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-02 13:57 [PATCH for-8.1 0/6] Fix endianness issues in the intel-iommu device Thomas Huth
2023-08-02 13:57 ` [PATCH 1/6] hw/i386/intel_iommu: Fix trivial endianness problems Thomas Huth
2023-08-02 21:13 ` Philippe Mathieu-Daudé
2023-08-02 13:57 ` [PATCH 2/6] hw/i386/intel_iommu: Fix endianness problems related to VTD_IR_TableEntry Thomas Huth
2023-08-02 13:57 ` Thomas Huth [this message]
2023-08-02 21:16 ` [PATCH 3/6] hw/i386/intel_iommu: Fix struct VTDInvDescIEC on big endian hosts Philippe Mathieu-Daudé
2023-08-02 13:57 ` [PATCH 4/6] hw/i386/intel_iommu: Fix index calculation in vtd_interrupt_remap_msi() Thomas Huth
2023-08-02 21:12 ` Philippe Mathieu-Daudé
2023-08-02 13:57 ` [PATCH 5/6] hw/i386/x86-iommu: Fix endianness issue in x86_iommu_irq_to_msi_message() Thomas Huth
2023-08-02 21:16 ` Philippe Mathieu-Daudé
2023-08-02 13:57 ` [PATCH 6/6] include/hw/i386/x86-iommu: Fix struct X86IOMMU_MSIMessage for big endian hosts Thomas Huth
2023-08-02 15:36 ` [PATCH for-8.1 0/6] Fix endianness issues in the intel-iommu device Peter Xu
2023-08-02 15:37 ` Michael S. Tsirkin
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