From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: jniethe5@gmail.com, qemu-ppc@nongnu.org, bgray@linux.ibm.com
Subject: [PATCH 4/7] tcg/ppc: Use PLD in tcg_out_movi for constant pool
Date: Fri, 4 Aug 2023 14:33:52 -0700 [thread overview]
Message-ID: <20230804213355.294443-5-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230804213355.294443-1-richard.henderson@linaro.org>
The prefixed instruction has a pc-relative form to use here.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target.c.inc | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index d41c499b7d..a9e48a51c8 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -101,6 +101,10 @@
#define ALL_GENERAL_REGS 0xffffffffu
#define ALL_VECTOR_REGS 0xffffffff00000000ull
+#ifndef R_PPC64_PCREL34
+#define R_PPC64_PCREL34 132
+#endif
+
#define have_isel (cpuinfo & CPUINFO_ISEL)
#ifndef CONFIG_SOFTMMU
@@ -260,6 +264,19 @@ static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
return false;
}
+static bool reloc_pc34(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
+{
+ const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
+ ptrdiff_t disp = tcg_ptr_byte_diff(target, src_rx);
+
+ if (disp == sextract64(disp, 0, 34)) {
+ src_rw[0] = (src_rw[0] & ~0x3ffff) | ((disp >> 16) & 0x3ffff);
+ src_rw[1] = (src_rw[1] & ~0xffff) | (disp & 0xffff);
+ return true;
+ }
+ return false;
+}
+
/* test if a constant matches the constraint */
static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
{
@@ -684,6 +701,8 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
return reloc_pc14(code_ptr, target);
case R_PPC_REL24:
return reloc_pc24(code_ptr, target);
+ case R_PPC64_PCREL34:
+ return reloc_pc34(code_ptr, target);
case R_PPC_ADDR16:
/*
* We are (slightly) abusing this relocation type. In particular,
@@ -1107,6 +1126,11 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
}
/* Use the constant pool, if possible. */
+ if (have_isa_3_10) {
+ tcg_out_8ls_d(s, PLD, ret, 0, 0, 1);
+ new_pool_label(s, arg, R_PPC64_PCREL34, s->code_ptr - 2, 0);
+ return;
+ }
if (!in_prologue && USE_REG_TB) {
new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr,
tcg_tbrel_diff(s, NULL));
--
2.34.1
next prev parent reply other threads:[~2023-08-04 21:35 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-04 21:33 [PATCH for-8.2 0/7] tcg/ppc: Support power10 prefixed instructions Richard Henderson
2023-08-04 21:33 ` [PATCH 1/7] tcg/ppc: Untabify tcg-target.c.inc Richard Henderson
2023-08-04 21:33 ` [PATCH 2/7] tcg/ppc: Use PADDI in tcg_out_movi Richard Henderson
2023-08-07 3:53 ` Jordan Niethe
2023-08-07 21:26 ` Richard Henderson
2023-08-04 21:33 ` [PATCH 3/7] tcg/ppc: Use prefixed instructions in tcg_out_mem_long Richard Henderson
2023-08-07 3:51 ` Jordan Niethe
2023-08-04 21:33 ` Richard Henderson [this message]
2023-08-04 21:33 ` [PATCH 5/7] tcg/ppc: Use prefixed instructions in tcg_out_dupi_vec Richard Henderson
2023-08-04 21:33 ` [PATCH 6/7] tcg/ppc: Disable USE_REG_TB for Power v3.1 Richard Henderson
2023-08-06 11:58 ` Nicholas Piggin
2023-08-06 13:45 ` Richard Henderson
2023-08-04 21:33 ` [PATCH 7/7] tcg/ppc: Use prefixed instructions for tcg_out_goto_tb Richard Henderson
2023-08-06 12:55 ` Nicholas Piggin
2023-08-06 14:13 ` Richard Henderson
2023-08-07 1:51 ` Nicholas Piggin
2023-08-07 7:29 ` Nicholas Piggin
2023-08-07 9:38 ` Nicholas Piggin
2023-08-07 4:08 ` Jordan Niethe
2023-08-06 11:55 ` [PATCH for-8.2 0/7] tcg/ppc: Support power10 prefixed instructions Nicholas Piggin
2023-08-06 14:22 ` Richard Henderson
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