[PATCH v2 1/5] target/loongarch: Add loongarch32 mode for loongarch64-softmmu

[PATCH v2 1/5] target/loongarch: Add loongarch32 mode for loongarch64-softmmu

[Jiajie Chen]

This commit adds loongarch32 mode to loongarch64-softmmu.

Signed-off-by: Jiajie Chen <c@jia.je>
---
 target/loongarch/cpu.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index fa371ca8ba..43c73e6363 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -272,9 +272,16 @@ struct LoongArchTLB {
 };
 typedef struct LoongArchTLB LoongArchTLB;
 
+/* Current LoongArch mode */
+typedef enum LoongArchMode {
+    LA32 = 0,
+    LA64 = 1,
+} LoongArchMode;
+
 typedef struct CPUArchState {
     uint64_t gpr[32];
     uint64_t pc;
+    LoongArchMode mode;
 
     fpr_t fpr[32];
     float_status fp_status;
-- 
2.39.2

[PATCH v2 2/5] target/loongarch: Add loongarch32 cpu la132

[Jiajie Chen]

Add la132 as a loongarch32 cpu type and allow virt machine to be used
with la132 instead of la464.

Signed-off-by: Jiajie Chen <c@jia.je>
---
 hw/loongarch/virt.c    |  5 -----
 target/loongarch/cpu.c | 41 +++++++++++++++++++++++++++++++++++++++++
 target/loongarch/cpu.h | 11 +++++++++++
 3 files changed, 52 insertions(+), 5 deletions(-)

diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index e19b042ce8..af15bf5aaa 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -798,11 +798,6 @@ static void loongarch_init(MachineState *machine)
         cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
     }
 
-    if (!strstr(cpu_model, "la464")) {
-        error_report("LoongArch/TCG needs cpu type la464");
-        exit(1);
-    }
-
     if (ram_size < 1 * GiB) {
         error_report("ram_size must be greater than 1G.");
         exit(1);
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index ad93ecac92..d31efe86da 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -362,6 +362,8 @@ static void loongarch_la464_initfn(Object *obj)
     CPULoongArchState *env = &cpu->env;
     int i;
 
+    env->mode = LA64;
+
     for (i = 0; i < 21; i++) {
         env->cpucfg[i] = 0x0;
     }
@@ -439,6 +441,20 @@ static void loongarch_la464_initfn(Object *obj)
     env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
 }
 
+static void loongarch_la132_initfn(Object *obj)
+{
+    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+    CPULoongArchState *env = &cpu->env;
+
+    env->mode = LA32;
+
+    cpu->dtb_compatible = "loongarch,Loongson-3C103";
+
+    uint32_t data = 0;
+    data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */
+    env->cpucfg[1] = data;
+}
+
 static void loongarch_cpu_list_entry(gpointer data, gpointer user_data)
 {
     const char *typename = object_class_get_name(OBJECT_CLASS(data));
@@ -732,6 +748,10 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
 #endif
 }
 
+static void loongarch32_cpu_class_init(ObjectClass *c, void *data)
+{
+}
+
 #define DEFINE_LOONGARCH_CPU_TYPE(model, initfn) \
     { \
         .parent = TYPE_LOONGARCH_CPU, \
@@ -754,3 +774,24 @@ static const TypeInfo loongarch_cpu_type_infos[] = {
 };
 
 DEFINE_TYPES(loongarch_cpu_type_infos)
+
+#define DEFINE_LOONGARCH32_CPU_TYPE(model, initfn) \
+    { \
+        .parent = TYPE_LOONGARCH32_CPU, \
+        .instance_init = initfn, \
+        .name = LOONGARCH_CPU_TYPE_NAME(model), \
+    }
+
+static const TypeInfo loongarch32_cpu_type_infos[] = {
+    {
+        .name = TYPE_LOONGARCH32_CPU,
+        .parent = TYPE_LOONGARCH_CPU,
+        .instance_size = sizeof(LoongArchCPU),
+
+        .abstract = true,
+        .class_size = sizeof(LoongArchCPUClass),
+        .class_init = loongarch32_cpu_class_init,
+    },
+    DEFINE_LOONGARCH32_CPU_TYPE("la132", loongarch_la132_initfn),
+};
+DEFINE_TYPES(loongarch32_cpu_type_infos)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 43c73e6363..f1907cddc5 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -404,6 +404,17 @@ struct LoongArchCPUClass {
     ResettablePhases parent_phases;
 };
 
+#define TYPE_LOONGARCH32_CPU "loongarch32-cpu"
+typedef struct LoongArch32CPUClass LoongArch32CPUClass;
+DECLARE_CLASS_CHECKERS(LoongArch32CPUClass, LOONGARCH32_CPU,
+                       TYPE_LOONGARCH32_CPU)
+
+struct LoongArch32CPUClass {
+    /*< private >*/
+    LoongArchCPUClass parent_class;
+    /*< public >*/
+};
+
 /*
  * LoongArch CPUs has 4 privilege levels.
  * 0 for kernel mode, 3 for user mode.
-- 
2.39.2

[PATCH v2 3/5] target/loongarch: Add GDB support for loongarch32 mode

[Jiajie Chen]

GPRs and PC are 32-bit wide in loongarch32 mode.

Signed-off-by: Jiajie Chen <c@jia.je>
---
 configs/targets/loongarch64-softmmu.mak |  2 +-
 gdb-xml/loongarch-base32.xml            | 45 +++++++++++++++++++++++++
 target/loongarch/cpu.c                  | 10 +++++-
 target/loongarch/gdbstub.c              | 32 ++++++++++++++----
 4 files changed, 80 insertions(+), 9 deletions(-)
 create mode 100644 gdb-xml/loongarch-base32.xml

diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loongarch64-softmmu.mak
index 9abc99056f..f23780fdd8 100644
--- a/configs/targets/loongarch64-softmmu.mak
+++ b/configs/targets/loongarch64-softmmu.mak
@@ -1,5 +1,5 @@
 TARGET_ARCH=loongarch64
 TARGET_BASE_ARCH=loongarch
 TARGET_SUPPORTS_MTTCG=y
-TARGET_XML_FILES= gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml
+TARGET_XML_FILES= gdb-xml/loongarch-base32.xml gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml
 TARGET_NEED_FDT=y
diff --git a/gdb-xml/loongarch-base32.xml b/gdb-xml/loongarch-base32.xml
new file mode 100644
index 0000000000..af47bbd3da
--- /dev/null
+++ b/gdb-xml/loongarch-base32.xml
@@ -0,0 +1,45 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2022 Free Software Foundation, Inc.
+
+     Copying and distribution of this file, with or without modification,
+     are permitted in any medium without royalty provided the copyright
+     notice and this notice are preserved.  -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.loongarch.base">
+  <reg name="r0" bitsize="32" type="uint32" group="general"/>
+  <reg name="r1" bitsize="32" type="code_ptr" group="general"/>
+  <reg name="r2" bitsize="32" type="data_ptr" group="general"/>
+  <reg name="r3" bitsize="32" type="data_ptr" group="general"/>
+  <reg name="r4" bitsize="32" type="uint32" group="general"/>
+  <reg name="r5" bitsize="32" type="uint32" group="general"/>
+  <reg name="r6" bitsize="32" type="uint32" group="general"/>
+  <reg name="r7" bitsize="32" type="uint32" group="general"/>
+  <reg name="r8" bitsize="32" type="uint32" group="general"/>
+  <reg name="r9" bitsize="32" type="uint32" group="general"/>
+  <reg name="r10" bitsize="32" type="uint32" group="general"/>
+  <reg name="r11" bitsize="32" type="uint32" group="general"/>
+  <reg name="r12" bitsize="32" type="uint32" group="general"/>
+  <reg name="r13" bitsize="32" type="uint32" group="general"/>
+  <reg name="r14" bitsize="32" type="uint32" group="general"/>
+  <reg name="r15" bitsize="32" type="uint32" group="general"/>
+  <reg name="r16" bitsize="32" type="uint32" group="general"/>
+  <reg name="r17" bitsize="32" type="uint32" group="general"/>
+  <reg name="r18" bitsize="32" type="uint32" group="general"/>
+  <reg name="r19" bitsize="32" type="uint32" group="general"/>
+  <reg name="r20" bitsize="32" type="uint32" group="general"/>
+  <reg name="r21" bitsize="32" type="uint32" group="general"/>
+  <reg name="r22" bitsize="32" type="data_ptr" group="general"/>
+  <reg name="r23" bitsize="32" type="uint32" group="general"/>
+  <reg name="r24" bitsize="32" type="uint32" group="general"/>
+  <reg name="r25" bitsize="32" type="uint32" group="general"/>
+  <reg name="r26" bitsize="32" type="uint32" group="general"/>
+  <reg name="r27" bitsize="32" type="uint32" group="general"/>
+  <reg name="r28" bitsize="32" type="uint32" group="general"/>
+  <reg name="r29" bitsize="32" type="uint32" group="general"/>
+  <reg name="r30" bitsize="32" type="uint32" group="general"/>
+  <reg name="r31" bitsize="32" type="uint32" group="general"/>
+  <reg name="orig_a0" bitsize="32" type="uint32" group="general"/>
+  <reg name="pc" bitsize="32" type="code_ptr" group="general"/>
+  <reg name="badv" bitsize="32" type="code_ptr" group="general"/>
+</feature>
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index d31efe86da..ee6d45f1b0 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -710,7 +710,13 @@ static const struct SysemuCPUOps loongarch_sysemu_ops = {
 
 static gchar *loongarch_gdb_arch_name(CPUState *cs)
 {
-    return g_strdup("loongarch64");
+    LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+    CPULoongArchState *env = &cpu->env;
+    if (env->mode == LA64) {
+        return g_strdup("loongarch64");
+    } else {
+        return g_strdup("loongarch32");
+    }
 }
 
 static void loongarch_cpu_class_init(ObjectClass *c, void *data)
@@ -750,6 +756,8 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
 
 static void loongarch32_cpu_class_init(ObjectClass *c, void *data)
 {
+    CPUClass *cc = CPU_CLASS(c);
+    cc->gdb_core_xml_file = "loongarch-base32.xml";
 }
 
 #define DEFINE_LOONGARCH_CPU_TYPE(model, initfn) \
diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c
index 0752fff924..7c82204e92 100644
--- a/target/loongarch/gdbstub.c
+++ b/target/loongarch/gdbstub.c
@@ -34,16 +34,25 @@ int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
 {
     LoongArchCPU *cpu = LOONGARCH_CPU(cs);
     CPULoongArchState *env = &cpu->env;
+    uint64_t val;
 
     if (0 <= n && n < 32) {
-        return gdb_get_regl(mem_buf, env->gpr[n]);
+        val = env->gpr[n];
     } else if (n == 32) {
         /* orig_a0 */
-        return gdb_get_regl(mem_buf, 0);
+        val = 0;
     } else if (n == 33) {
-        return gdb_get_regl(mem_buf, env->pc);
+        val = env->pc;
     } else if (n == 34) {
-        return gdb_get_regl(mem_buf, env->CSR_BADV);
+        val = env->CSR_BADV;
+    }
+
+    if (0 <= n && n <= 34) {
+        if (env->mode == LA64) {
+            return gdb_get_reg64(mem_buf, val);
+        } else {
+            return gdb_get_reg32(mem_buf, val);
+        }
     }
     return 0;
 }
@@ -52,15 +61,24 @@ int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
 {
     LoongArchCPU *cpu = LOONGARCH_CPU(cs);
     CPULoongArchState *env = &cpu->env;
-    target_ulong tmp = ldtul_p(mem_buf);
+    target_ulong tmp;
+    int read_length;
     int length = 0;
 
+    if (env->mode == LA64) {
+        tmp = ldq_p(mem_buf);
+        read_length = 8;
+    } else {
+        tmp = ldl_p(mem_buf);
+        read_length = 4;
+    }
+
     if (0 <= n && n < 32) {
         env->gpr[n] = tmp;
-        length = sizeof(target_ulong);
+        length = read_length;
     } else if (n == 33) {
         env->pc = tmp;
-        length = sizeof(target_ulong);
+        length = read_length;
     }
     return length;
 }
-- 
2.39.2

[PATCH v2 4/5] target/loongarch: Support LoongArch32 TLB entry

[Jiajie Chen]

The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
zero in LoongArch32.

Signed-off-by: Jiajie Chen <c@jia.je>
---
 target/loongarch/cpu-csr.h    |  9 +++++----
 target/loongarch/tlb_helper.c | 17 ++++++++++++-----
 2 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
index f8f24032cb..faf76a589b 100644
--- a/target/loongarch/cpu-csr.h
+++ b/target/loongarch/cpu-csr.h
@@ -66,10 +66,11 @@ FIELD(TLBENTRY, D, 1, 1)
 FIELD(TLBENTRY, PLV, 2, 2)
 FIELD(TLBENTRY, MAT, 4, 2)
 FIELD(TLBENTRY, G, 6, 1)
-FIELD(TLBENTRY, PPN, 12, 36)
-FIELD(TLBENTRY, NR, 61, 1)
-FIELD(TLBENTRY, NX, 62, 1)
-FIELD(TLBENTRY, RPLV, 63, 1)
+FIELD(TLBENTRY_32, PPN, 12, 24)
+FIELD(TLBENTRY_64, PPN, 12, 36)
+FIELD(TLBENTRY_64, NR, 61, 1)
+FIELD(TLBENTRY_64, NX, 62, 1)
+FIELD(TLBENTRY_64, RPLV, 63, 1)
 
 #define LOONGARCH_CSR_ASID           0x18 /* Address space identifier */
 FIELD(CSR_ASID, ASID, 0, 10)
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
index 6e00190547..690c6ef25f 100644
--- a/target/loongarch/tlb_helper.c
+++ b/target/loongarch/tlb_helper.c
@@ -48,10 +48,17 @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
     tlb_v = FIELD_EX64(tlb_entry, TLBENTRY, V);
     tlb_d = FIELD_EX64(tlb_entry, TLBENTRY, D);
     tlb_plv = FIELD_EX64(tlb_entry, TLBENTRY, PLV);
-    tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY, PPN);
-    tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY, NX);
-    tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY, NR);
-    tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY, RPLV);
+    if (env->mode == LA64) {
+        tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_64, PPN);
+        tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY_64, NX);
+        tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY_64, NR);
+        tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY_64, RPLV);
+    } else {
+        tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_32, PPN);
+        tlb_nx = 0;
+        tlb_nr = 0;
+        tlb_rplv = 0;
+    }
 
     /* Check access rights */
     if (!tlb_v) {
@@ -79,7 +86,7 @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
      * tlb_entry contains ppn[47:12] while 16KiB ppn is [47:15]
      * need adjust.
      */
-    *physical = (tlb_ppn << R_TLBENTRY_PPN_SHIFT) |
+    *physical = (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) |
                 (address & MAKE_64BIT_MASK(0, tlb_ps));
     *prot = PAGE_READ;
     if (tlb_d) {
-- 
2.39.2

[PATCH v2 5/5] target/loongarch: Support LoongArch32 DMW

[Jiajie Chen]

LA32 uses a different encoding for CSR.DMW and a new direct mapping
mechanism.

Signed-off-by: Jiajie Chen <c@jia.je>
---
 target/loongarch/cpu-csr.h    |  7 +++----
 target/loongarch/tlb_helper.c | 26 +++++++++++++++++++++++---
 2 files changed, 26 insertions(+), 7 deletions(-)

diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
index faf76a589b..72cac5fff9 100644
--- a/target/loongarch/cpu-csr.h
+++ b/target/loongarch/cpu-csr.h
@@ -188,10 +188,9 @@ FIELD(CSR_DMW, PLV1, 1, 1)
 FIELD(CSR_DMW, PLV2, 2, 1)
 FIELD(CSR_DMW, PLV3, 3, 1)
 FIELD(CSR_DMW, MAT, 4, 2)
-FIELD(CSR_DMW, VSEG, 60, 4)
-
-#define dmw_va2pa(va) \
-    (va & MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS))
+FIELD(CSR_DMW_32, PSEG, 25, 3)
+FIELD(CSR_DMW_32, VSEG, 29, 3)
+FIELD(CSR_DMW_64, VSEG, 60, 4)
 
 /* Debug CSRs */
 #define LOONGARCH_CSR_DBG            0x500 /* debug config */
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
index 690c6ef25f..ea78108aff 100644
--- a/target/loongarch/tlb_helper.c
+++ b/target/loongarch/tlb_helper.c
@@ -173,6 +173,18 @@ static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
     return TLBRET_NOMATCH;
 }
 
+static hwaddr dmw_va2pa(CPULoongArchState *env, target_ulong va,
+                        target_ulong dmw)
+{
+    if (env->mode == LA64) {
+        return va & TARGET_PHYS_MASK;
+    } else {
+        uint32_t pseg = FIELD_EX32(dmw, CSR_DMW_32, PSEG);
+        return (va & MAKE_64BIT_MASK(0, R_CSR_DMW_32_VSEG_SHIFT)) | \
+            (pseg << R_CSR_DMW_32_VSEG_SHIFT);
+    }
+}
+
 static int get_physical_address(CPULoongArchState *env, hwaddr *physical,
                                 int *prot, target_ulong address,
                                 MMUAccessType access_type, int mmu_idx)
@@ -192,12 +204,20 @@ static int get_physical_address(CPULoongArchState *env, hwaddr *physical,
     }
 
     plv = kernel_mode | (user_mode << R_CSR_DMW_PLV3_SHIFT);
-    base_v = address >> R_CSR_DMW_VSEG_SHIFT;
+    if (env->mode == LA64) {
+        base_v = address >> R_CSR_DMW_64_VSEG_SHIFT;
+    } else {
+        base_v = (uint32_t)address >> R_CSR_DMW_32_VSEG_SHIFT;
+    }
     /* Check direct map window */
     for (int i = 0; i < 4; i++) {
-        base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW, VSEG);
+        if (env->mode == LA64) {
+            base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW_64, VSEG);
+        } else {
+            base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW_32, VSEG);
+        }
         if ((plv & env->CSR_DMW[i]) && (base_c == base_v)) {
-            *physical = dmw_va2pa(address);
+            *physical = dmw_va2pa(env, address, env->CSR_DMW[i]);
             *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
             return TLBRET_MATCH;
         }
-- 
2.39.2

Re: [PATCH v2 4/5] target/loongarch: Support LoongArch32 TLB entry

[Jiajie Chen]

On 2023/8/7 11:18, Jiajie Chen wrote:
> The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
> zero in LoongArch32.
>
> Signed-off-by: Jiajie Chen <c@jia.je>
> ---
>   target/loongarch/cpu-csr.h    |  9 +++++----
>   target/loongarch/tlb_helper.c | 17 ++++++++++++-----
>   2 files changed, 17 insertions(+), 9 deletions(-)
>
> diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
> index f8f24032cb..faf76a589b 100644
> --- a/target/loongarch/cpu-csr.h
> +++ b/target/loongarch/cpu-csr.h
> @@ -66,10 +66,11 @@ FIELD(TLBENTRY, D, 1, 1)
>   FIELD(TLBENTRY, PLV, 2, 2)
>   FIELD(TLBENTRY, MAT, 4, 2)
>   FIELD(TLBENTRY, G, 6, 1)
> -FIELD(TLBENTRY, PPN, 12, 36)
> -FIELD(TLBENTRY, NR, 61, 1)
> -FIELD(TLBENTRY, NX, 62, 1)
> -FIELD(TLBENTRY, RPLV, 63, 1)
> +FIELD(TLBENTRY_32, PPN, 12, 24)

Sorry, the starting bit of TLBENTRY_32_PPN should be 8 instead of 12. 
Will be corrected in v3.


> +FIELD(TLBENTRY_64, PPN, 12, 36)
> +FIELD(TLBENTRY_64, NR, 61, 1)
> +FIELD(TLBENTRY_64, NX, 62, 1)
> +FIELD(TLBENTRY_64, RPLV, 63, 1)
>   
>   #define LOONGARCH_CSR_ASID           0x18 /* Address space identifier */
>   FIELD(CSR_ASID, ASID, 0, 10)
> diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
> index 6e00190547..690c6ef25f 100644
> --- a/target/loongarch/tlb_helper.c
> +++ b/target/loongarch/tlb_helper.c
> @@ -48,10 +48,17 @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
>       tlb_v = FIELD_EX64(tlb_entry, TLBENTRY, V);
>       tlb_d = FIELD_EX64(tlb_entry, TLBENTRY, D);
>       tlb_plv = FIELD_EX64(tlb_entry, TLBENTRY, PLV);
> -    tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY, PPN);
> -    tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY, NX);
> -    tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY, NR);
> -    tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY, RPLV);
> +    if (env->mode == LA64) {
> +        tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_64, PPN);
> +        tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY_64, NX);
> +        tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY_64, NR);
> +        tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY_64, RPLV);
> +    } else {
> +        tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_32, PPN);
> +        tlb_nx = 0;
> +        tlb_nr = 0;
> +        tlb_rplv = 0;
> +    }
>   
>       /* Check access rights */
>       if (!tlb_v) {
> @@ -79,7 +86,7 @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
>        * tlb_entry contains ppn[47:12] while 16KiB ppn is [47:15]
>        * need adjust.
>        */
> -    *physical = (tlb_ppn << R_TLBENTRY_PPN_SHIFT) |
> +    *physical = (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) |
>                   (address & MAKE_64BIT_MASK(0, tlb_ps));
>       *prot = PAGE_READ;
>       if (tlb_d) {

Re: [PATCH v2 4/5] target/loongarch: Support LoongArch32 TLB entry

[gaosong]

Hi, Jiajie

在 2023/8/7 下午1:17, Jiajie Chen 写道:
> 
> On 2023/8/7 11:18, Jiajie Chen wrote:
>> The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
>> zero in LoongArch32.
>>
>> Signed-off-by: Jiajie Chen <c@jia.je>
>> ---
>>   target/loongarch/cpu-csr.h    |  9 +++++----
>>   target/loongarch/tlb_helper.c | 17 ++++++++++++-----
>>   2 files changed, 17 insertions(+), 9 deletions(-)
>>
Please
Cc: Richard Henderson <richard.henderson@linaro.org>

And
Cc: Jun Yi <yijun@loongson.cn>
CC: shenjinyang@loongson.cn>
Their are also interested with Loongarch32 softmmu.

It would be better use the parameter '--cover-letter' create a patch0.
Add some Change logs and introduction about this series in patch0.

Thanks.
Song Gao
>> diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
>> index f8f24032cb..faf76a589b 100644
>> --- a/target/loongarch/cpu-csr.h
>> +++ b/target/loongarch/cpu-csr.h
>> @@ -66,10 +66,11 @@ FIELD(TLBENTRY, D, 1, 1)
>>   FIELD(TLBENTRY, PLV, 2, 2)
>>   FIELD(TLBENTRY, MAT, 4, 2)
>>   FIELD(TLBENTRY, G, 6, 1)
>> -FIELD(TLBENTRY, PPN, 12, 36)
>> -FIELD(TLBENTRY, NR, 61, 1)
>> -FIELD(TLBENTRY, NX, 62, 1)
>> -FIELD(TLBENTRY, RPLV, 63, 1)
>> +FIELD(TLBENTRY_32, PPN, 12, 24)
> 
> Sorry, the starting bit of TLBENTRY_32_PPN should be 8 instead of 12. 
> Will be corrected in v3.
> 
> 
>> +FIELD(TLBENTRY_64, PPN, 12, 36)
>> +FIELD(TLBENTRY_64, NR, 61, 1)
>> +FIELD(TLBENTRY_64, NX, 62, 1)
>> +FIELD(TLBENTRY_64, RPLV, 63, 1)
>>   #define LOONGARCH_CSR_ASID           0x18 /* Address space 
>> identifier */
>>   FIELD(CSR_ASID, ASID, 0, 10)
>> diff --git a/target/loongarch/tlb_helper.c 
>> b/target/loongarch/tlb_helper.c
>> index 6e00190547..690c6ef25f 100644
>> --- a/target/loongarch/tlb_helper.c
>> +++ b/target/loongarch/tlb_helper.c
>> @@ -48,10 +48,17 @@ static int 
>> loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
>>       tlb_v = FIELD_EX64(tlb_entry, TLBENTRY, V);
>>       tlb_d = FIELD_EX64(tlb_entry, TLBENTRY, D);
>>       tlb_plv = FIELD_EX64(tlb_entry, TLBENTRY, PLV);
>> -    tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY, PPN);
>> -    tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY, NX);
>> -    tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY, NR);
>> -    tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY, RPLV);
>> +    if (env->mode == LA64) {
>> +        tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_64, PPN);
>> +        tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY_64, NX);
>> +        tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY_64, NR);
>> +        tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY_64, RPLV);
>> +    } else {
>> +        tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_32, PPN);
>> +        tlb_nx = 0;
>> +        tlb_nr = 0;
>> +        tlb_rplv = 0;
>> +    }
>>       /* Check access rights */
>>       if (!tlb_v) {
>> @@ -79,7 +86,7 @@ static int loongarch_map_tlb_entry(CPULoongArchState 
>> *env, hwaddr *physical,
>>        * tlb_entry contains ppn[47:12] while 16KiB ppn is [47:15]
>>        * need adjust.
>>        */
>> -    *physical = (tlb_ppn << R_TLBENTRY_PPN_SHIFT) |
>> +    *physical = (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) |
>>                   (address & MAKE_64BIT_MASK(0, tlb_ps));
>>       *prot = PAGE_READ;
>>       if (tlb_d) {

Re: [PATCH v2 4/5] target/loongarch: Support LoongArch32 TLB entry

[Jiajie Chen]

On 2023/8/7 14:55, gaosong wrote:
> Hi, Jiajie
>
> 在 2023/8/7 下午1:17, Jiajie Chen 写道:
>>
>> On 2023/8/7 11:18, Jiajie Chen wrote:
>>> The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
>>> zero in LoongArch32.
>>>
>>> Signed-off-by: Jiajie Chen <c@jia.je>
>>> ---
>>>   target/loongarch/cpu-csr.h    |  9 +++++----
>>>   target/loongarch/tlb_helper.c | 17 ++++++++++++-----
>>>   2 files changed, 17 insertions(+), 9 deletions(-)
>>>
> Please
> Cc: Richard Henderson <richard.henderson@linaro.org>
>
> And
> Cc: Jun Yi <yijun@loongson.cn>
> CC: shenjinyang@loongson.cn>
> Their are also interested with Loongarch32 softmmu.
>
> It would be better use the parameter '--cover-letter' create a patch0.
> Add some Change logs and introduction about this series in patch0.

Thanks, I will add this in my next version of patch series.

> Thanks.
> Song Gao
>>> diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
>>> index f8f24032cb..faf76a589b 100644
>>> --- a/target/loongarch/cpu-csr.h
>>> +++ b/target/loongarch/cpu-csr.h
>>> @@ -66,10 +66,11 @@ FIELD(TLBENTRY, D, 1, 1)
>>>   FIELD(TLBENTRY, PLV, 2, 2)
>>>   FIELD(TLBENTRY, MAT, 4, 2)
>>>   FIELD(TLBENTRY, G, 6, 1)
>>> -FIELD(TLBENTRY, PPN, 12, 36)
>>> -FIELD(TLBENTRY, NR, 61, 1)
>>> -FIELD(TLBENTRY, NX, 62, 1)
>>> -FIELD(TLBENTRY, RPLV, 63, 1)
>>> +FIELD(TLBENTRY_32, PPN, 12, 24)
>>
>> Sorry, the starting bit of TLBENTRY_32_PPN should be 8 instead of 12. 
>> Will be corrected in v3.
>>
>>
>>> +FIELD(TLBENTRY_64, PPN, 12, 36)
>>> +FIELD(TLBENTRY_64, NR, 61, 1)
>>> +FIELD(TLBENTRY_64, NX, 62, 1)
>>> +FIELD(TLBENTRY_64, RPLV, 63, 1)
>>>   #define LOONGARCH_CSR_ASID           0x18 /* Address space 
>>> identifier */
>>>   FIELD(CSR_ASID, ASID, 0, 10)
>>> diff --git a/target/loongarch/tlb_helper.c 
>>> b/target/loongarch/tlb_helper.c
>>> index 6e00190547..690c6ef25f 100644
>>> --- a/target/loongarch/tlb_helper.c
>>> +++ b/target/loongarch/tlb_helper.c
>>> @@ -48,10 +48,17 @@ static int 
>>> loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
>>>       tlb_v = FIELD_EX64(tlb_entry, TLBENTRY, V);
>>>       tlb_d = FIELD_EX64(tlb_entry, TLBENTRY, D);
>>>       tlb_plv = FIELD_EX64(tlb_entry, TLBENTRY, PLV);
>>> -    tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY, PPN);
>>> -    tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY, NX);
>>> -    tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY, NR);
>>> -    tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY, RPLV);
>>> +    if (env->mode == LA64) {
>>> +        tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_64, PPN);
>>> +        tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY_64, NX);
>>> +        tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY_64, NR);
>>> +        tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY_64, RPLV);
>>> +    } else {
>>> +        tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_32, PPN);
>>> +        tlb_nx = 0;
>>> +        tlb_nr = 0;
>>> +        tlb_rplv = 0;
>>> +    }
>>>       /* Check access rights */
>>>       if (!tlb_v) {
>>> @@ -79,7 +86,7 @@ static int 
>>> loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
>>>        * tlb_entry contains ppn[47:12] while 16KiB ppn is [47:15]
>>>        * need adjust.
>>>        */
>>> -    *physical = (tlb_ppn << R_TLBENTRY_PPN_SHIFT) |
>>> +    *physical = (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) |
>>>                   (address & MAKE_64BIT_MASK(0, tlb_ps));
>>>       *prot = PAGE_READ;
>>>       if (tlb_d) {
>